Segger J-Link User Manual page 273

PIN SIGNAL
15 RESET
17 DBGRQ
5V-Sup-
19
ply
Table 10.1: J-Link / J-Trace pinout
Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They
should also be connected to GND in the target system.
10.1.1.1 Target board design
We strongly advise following the recommendations given by the chip manufacturer.
These recommendations are normally in line with the recommendations given in the
table Pinout for JTAG on page 272. In case of doubt you should follow the recommen-
dations given by the semiconductor manufacturer.
You may take any female header following the specifications of DIN 41651.
For example:
Harting
Molex
Tyco Electronics
J-Link / J-Trace (UM08001)
TYPE
Target CPU reset signal. Typically connected to the RESET
I/O pin of the target CPU, which is typically called "nRST",
"nRESET" or "RESET".
This pin is not connected in J-Link. It is reserved for com-
patibility with other equipment to be used as a debug
NC
request signal to the target system. Typically connected to
DBGRQ if available, otherwise left open.
This pin can be used to supply power to the target hard-
ware. Older J-Links may not be able to supply power on this
Output pin. For more information about how to enable/disable the
power supply, please refer to Target power supply on
page 274.
part-no. 09185206803
part-no. 90635-1202
part-no. 2-215882-0
Description
© 2004-2013 SEGGER Microcontroller GmbH & Co. KG
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