Jtag; Test Access Port (Tap); Data Registers; Instruction Register - Segger J-Link User Manual

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11.1 JTAG

JTAG is the acronym for Joint Test Action Group. In the scope of this document,
"the JTAG standard" means compliance with IEEE Standard 1149.1-2001.

11.1.1 Test access port (TAP)

JTAG defines a TAP (Test access port). The TAP is a general-purpose port that can
provide access to many test support functions built into a component. It is composed
as a minimum of the three input connections (TDI, TCK, TMS) and one output con-
nection (TDO). An optional fourth input connection (nTRST) provides for asynchro-
nous initialization of the test logic.
PIN
TCK
TDI
TMS
TDO
nTRST
Table 11.1: Test access port

11.1.2 Data registers

JTAG requires at least two data registers to be present: the bypass and the bound-
ary-scan register. Other registers are allowed but are not obligatory.
Bypass data register
A single-bit register that passes information from TDI to TDO.
Boundary-scan data register
A test data register which allows the testing of board interconnections, access to
input and output of components when testing their system logic and so on.

11.1.3 Instruction register

The instruction register holds the current instruction and its content is used by the
TAP controller to decide which test to perform or which data register to access. It
consist of at least two shift-register cells.
J-Link / J-Trace (UM08001)
Type
The test clock input (TCK) provides the clock for the test
Input
logic.
Serial test instructions and data are received by the test
Input
logic at test data input (TDI).
The signal received at test mode select (TMS) is
Input
decoded by the TAP controller to control test operations.
Test data output (TDO) is the serial output for test
Output
instructions and data from the test logic.
Input The optional test reset (nTRST) input provides for asyn-
(optional) chronous initialization of the TAP controller.
CHAPTER 11
Explanation
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Background information