Segger J-Link User Manual page 158

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5.8.1.4 Type 3: No reset
No reset is performed. Nothing happens.
5.8.1.5 Type 4: Hardware, halt with WP
The hardware RESET pin is used to reset the CPU. After reset release, J-Link continu-
ously tries to halt the CPU using a watchpoint. This typically halts the CPU shortly
after reset release; the CPU can in most systems execute some instructions before it
is halted.
The number of instructions executed depends primarily on the JTAG speed: the
higher the JTAG speed, the faster the CPU can be halted. Some CPUs can actually be
halted before executing any instruction, because the start of the CPU is delayed after
reset release
5.8.1.6 Type 5: Hardware, halt with DBGRQ
The hardware RESET pin is used to reset the CPU. After reset release, J-Link continu-
ously tries to halt the CPU using the DBGRQ. This typically halts the CPU shortly after
reset release; the CPU can in most systems execute some instructions before it is
halted.
The number of instructions executed depends primarily on the JTAG speed: the
higher the JTAG speed, the faster the CPU can be halted. Some CPUs can actually be
halted before executing any instruction, because the start of the CPU is delayed after
reset release.
5.8.1.7 Type 6: Software
This reset strategy is only a software reset. "Software reset" means basically no
reset, just changing the CPU registers such as PC and CPSR. This reset strategy sets
the CPU registers to their after-Reset values:
• PC = 0
• CPSR = 0xD3 (Supervisor mode, ARM, IRQ / FIQ disabled)
• All SPSR registers = 0x10
• All other registers (which are unpredictable after reset) are set to 0.
• The hardware RESET pin is not affected.
5.8.1.8 Type 7: Reserved
Reserved reset type.
5.8.1.9 Type 8: Software, for ATMEL AT91SAM7 MCUs
The reset pin of the device is disabled by default. This means that the reset strate-
gies which rely on the reset pin (low pulse on reset) do not work by default. For this
reason a special reset strategy has been made available.
It is recommended to use this reset strategy. This special reset strategy resets the
peripherals by writing to the RSTC_CR register. Resetting the peripherals puts all
peripherals in the defined reset state. This includes memory mapping register, which
means that after reset flash is mapped to address 0. It is also possible to achieve the
same effect by writing 0x4 to the RSTC_CR register located at address 0xfffffd00.
5.8.1.10 Type 9: Hardware, for NXP LPC MCUs
After reset a bootloader is mapped at address 0 on ARM 7 LPC devices. This reset
strategy performs a reset via reset strategy Type 1 in order to reset the CPU. It also
ensures that flash is mapped to address 0 by writing the MEMMAP register of the LPC.
This reset strategy is the recommended one for all ARM 7 LPC devices.
J-Link / J-Trace (UM08001)
CHAPTER 5
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Working with J-Link and J-Trace