Testing The Clock Section; Testing The Output Section - Symmetricom SSU-2000 User Manual

Synchronization supply unit and synchronization distribution unit
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3. Reconnect the input signal and verify that the LOS condition is cleared and the
reference input is selected according to the system configuration. This depends
on the setting for Revertive Selection, Input Priorities, and Reference Selection
mode.
4. Type
EVENT
recorded in the event log.

Testing the Clock Section

To test the clock section:
1. Type
CLK
The system displays the clocks by module position (1A1 for Clock A and 1A12 for
Clock B) and the status for each clock (SEL for the selected clock and OK for the
standby clock).
2. Verify that the PLL mode for each clock is in LOCK at this time, and that the Tau
value is at the maximum time constant set for each clock, dependent on the clock
type of ST2 or ST3E.
The PQL should be the level the clock is supplying to the output modules,
dependent on the reference input when in lock mode. The frequency offset
depends on the clock type, and is typically less than 2E-10 for ST2, 1E-6 for
ST3E, and less than 2E-07 for TYPEI clocks. This only indicates the uncorrected
frequency offset of the oscillator which is being removed by the clock DDS
circuitry.
The sigma value indicates the stability of the clock, which should be less than
1E-9.

Testing the Output Section

To test the output section:
1. Type
OUTPUT
alarms. This will display the output modules by position with module status OK
and the selected clock. The clock status will indicate the presence or absence of
the four possible clocks: A, B, C (bypass), or D (expansion shelf only).
2. Verify that any outputs configured for redundant pairs are so indicated in the
status report. The PQL will indicate the output SSM level for all ports and is
supplied by the selected clock.
3. Verify that all output ports which are intended to be active indicate Y in the port
status.
12713020-002-2 Revision F.01 – January 2007
and press Enter; verify that the alarms and events created are
and press Enter to verify each clock is operating properly.
and press Enter to verify each output module is operating with no
Chapter 4 Commissioning
Commissioning Tests
SSU-2000 User's Guide 125

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