GE VAT200 Quick Start Manual page 66

Parameter Group 7 - Analog input signal operation mode
Analog Input Signal Operation Mode:
7-00:AIN Gain(%) 0 - 200
7-01:AIN Bias(%) 0 - 100
7-02:AIN Bias Selection: 0000:positive
7-03:AIN Slope: 0000:positive
7-04: AIN signal verification Scan Time (AIN, AI2) 1–100 ( × 4mSec)
7-05: AI2 Gain (%)(S6) 0 – 200
1. 7-02 = 0 ： 0V(0mA) corresponding to Lower Frequency Limit. ， 10V (20mA) corresponding to Upper
Frequency Limit.
2. 7-02 = 1 ： 10V(20mA) corresponding to Lower Frequency Limit ， 0V (0mA) corresponding to Upper
Frequency Limit.
3 .12-6 = 0 ： 0~10V(0~20mA)
= 1 ： 2~10V(4~20mA)
The setting of figure 1:
7-00 7-01
100 ﹪
A 50%
100 ﹪
B 0%
Figure 1
Hz
Bias
100%
60Hz
50%
30Hz
0Hz
0V
(0mA)
The setting of figure 3:
7-00 7-01
100 ﹪
E 20%
Hz
60Hz
30Hz
Bias
0%
0Hz
-50%
-100%
3. The inverter reads the average value of A/D signals once per (7-04×4ms). Users can determine scan
intervals according to noise in the environment. Increase 7-04 in noisy environment, but the respond
time will increase accordingly.
0001:Negative
F = I* (3 -0 0 )/ 2 0
F =(I -4 )* (3 -0 0 ) /1 6 I> =4 ； SW 2 = Ｉ
F =0
F =(V-2 )* (3 -0 0 ) /8 V > =2 ； SW 2 =V o r
F =0
7-02 7-03 7-05
0 0 100%
0 0 100%
Upper Frequency
A
B
V
10V
5V
(20mA)
7-02 7-03 7-05
1 0 100%
Figure 3
Upper Frequency Limit
(3-00=60)
E
V
2V 10V
(4mA)
(20mA)
0001:Negative
I > =0 ； SW 2 = Ｉ o r F =V * (3 -0 0 ) /1 0
I <4
V <2
The setting of figure2:
7-00
100 ﹪
C
100 ﹪
D
Bias
60Hz
100%
50%
30Hz
The setting of figure 4:
7-00
100 ﹪ 50%
F
Bias
-0%
-50%
-100%
4-40
Chapter 4 Software Index
V >= 0 ； SW 2 =V
7-01 7-02 7-03
50% 0 1
0% 0 1
Figure 2
Hz
Upper Frequency Limit
C
(3-00=60)
D
0Hz
0V
5V
10V
(0mA)
(20mA)
7-01 7-02 7-03
１
1
Hz
Figure 4
60Hz
Upper Frequency Limit
(3-00=60)
30Hz
F
0Hz
10V
5V
(20mA)
7-05
100%
100%
V
7-05
100%
V