Dram Memory; Table 3-4. Pci To Ecc Memory Access Timing - Motorola MVME2301 Installation And Use Manual

Table 3-4. PCI to ECC Memory Access Timing

Access Type
64-bit Burst Reads
64-bit Burst Writes
32-bit Burst Reads
32-bit Burst Writes
1-Beat Read
1-Beat Write
Notes 1. The latency assumes two system clocks for 60X

DRAM Memory

The MVME2300 DRAM memory size can be 16MB, 32MB, 64MB, or
128MB.
The DRAM blocks are controlled by the Falcon chipset which
performs two-way interleaving and provides single-bit error
correction and double-bit error correction. ECC is calculated over
72-bits.
PCI Clock Periods Required for:
1st Beat 2nd Beat
10 1
3 1
10 1
3 1
10 -
-
3
system bus arbitration.
2. The latency is based on 60ns, fast-page DRAM
timing. It is also assumed that L2 is either disabled or
missed.
3. Write timings assume write posting FIFO is initially
empty.
Functional Description
3rd Beat nth Beat
1 1
1 1
1 1
1 1
- -
- -
3
Maximum
Bandwidth
3-7