Dram; Sram; Eprom - Motorola MVME167P Installation And Use Manual

Functional Description

DRAM

5

SRAM

EPROM

5-6
MVME167P boards are built with 16MB, 32MB or 64MB synchronous
DRAM (SDRAM). The MVME167P have the SDRAM configured to
model 4MB, 8MB, 16MB, 32MB, or 64MB of ECC-protected DRAM.
The SDRAM memory array itself is always a single-bit error correcting
and multi-bit error detection memory, irrespective of which interface
model you use to access the SDRAM.
For specifics on SDRAM performance and for detailed programming
information, refer to the chapters on MCECC memory controller
emulations in the MVME1X7P Single Board Computers Programmer's
Reference Guide.
The MVME167P implementation includes 128KB SRAM (static RAM).
SRAM architecture is single non-interleaved.
SRAM performance is described in the section on the SRAM memory
interface in the MVME1X7P Single Board Computers Programmer's
Reference Guide. Battery backup options are selected via jumper header
J9.
There are four 44-pin PLCC/CLCC EPROM sockets for 27C102JK or
27C202JK type EPROMs. They are organized as two 32-bit wide banks
that support 8-, 16-, and 32-bit read accesses. The EPROMs are mapped to
local bus address 0 following a local bus reset. This allows the MC68040
to access the stack pointer and execution address following a reset.
The EPROMs are controlled by the VMEchip2 ASIC. The map decoder,
the access time, and the time when they appear at address 0 are
programmable. For more detail, refer to the VMEchip2 description in the
MVME1X7P Single Board Computers Programmer's Reference Guide.
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