Core Debug - Xilinx SMPTE 2022-5/6 Product Manual

Core Debug

Crucial Register Settings
1. Ensure bits [31:0] of network_path_differential (0x028) and bits [31:0]
playout_delay (0x11C) registers are set accordingly.
2. Ensure media_pkt_buf_size (0x130) is enough based on media buffer size formula
showed in Memory Requirement and Register Configurations in Chapter
3. Ensure the fec_buf_base_addr (0x034) register and media_buf_base_addr
(0x12C) register are set accordingly and not overlapping.
4. Ensure the match_sel (0x0B4) register is set properly to match the Ethernet Header
(SSRC, IP Source, IP Destination, UDP Source, UDP Destination and VLAN TAG ID) which
is set in the core and indicates which channel it belongs.
Debug Operation
1. If pri_recv_pkt_cnt (0x03C) register and sec_recv_pkt_cnt (0x040) register is
incrementing, it indicates the core is receiving packets.
2. If pri_discard_pkt_cnt (0x04C) register and sec_discard_pkt_cnt (0x050)
register is incrementing, it indicates the incoming packets is dropped due it doesn't
match with the settings of match_sel (0x0B4) register.
3. Ensure the bit [0] packet lock of sdi_pkt_status (0x114) register is high which
indicates the core has locked to a packet.
4. If link_valid_media_pkt_cnt (0x0C0) register and
chan_valid_media_pkt_cnt (0x134) register is incrementing, it indicate valid
packet is coming into the core.
5. If oor_pkts_cnt (0x160) register is incrementing, it indicates dropped packet due the
incoming packet timestamp falls outside the window as set by bits [31:9] of
network_path_differential (0x028) and bits [31:9] of playout_delay (0x11C)
registers.
6. Ensure that the curr_pkts_buffered (0x140) is not greater than the
media_pkt_buf_size (0x130) register.
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
www.xilinx.com
Appendix C: Debugging
3.
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