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MATCH_SRC_IP_ADDR (0x09C) Register
This parameter is used in filtering the packets for the channel. Configure Bit 31-0 for Source
IP address matching.
MATCH_SRC_PORT (0x0AC) Register
This parameter is used in filtering the packets for the channel. Configure Bit 15-0 for UDP
Source Port matching.
MATCH_DEST_PORT (0x0B0) Register
This parameter is used in filtering the packets for the channel. Configure Bit 15-0 for UDP
Destination Port matching.
MATCH_SEL (0x0B4) Register
This register sets the parameters to match the incoming packet and filter it to the channel.
•
Bit 5 matches the SSRC field in the RTP header of the packet to the configured register
0x110.
•
Bit 4 matches the Destination Port field in the UDP header of the packet to the
configured register 0x0B0.
•
Bit 3 matches the Source Port field in the UDP header of the packet to the configured
register 0x0AC.
•
Bit 2 matches the Destination address field in the IP header of the packet to the
configured register 0x08C.
•
Bit 1 matches the Source address field in the IP header of the packet to the configured
register 0x09C.
•
Bit 0 matches the IEEE 802.1Q tag in the Ethernet frame to the configured register
0x088.
Note that each link media packet can only be filtered into 1 particular channel.
LINK_REORDERED_PKT_CNT (0x0B8) Register
This counter tracks the number of incoming media packets that are reordered in the link
channel (primary or secondary). A packet is considered reorder when its sequence number
is less than the previous packet. Register 0x0BC, bit 0 resets the counter.
LINK_STAT_RESET (0x0BC) Register
•
A High to Bit 1 resets link valid media packet counter (register 0x0C0).
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
www.xilinx.com
Chapter 2: Product Specification
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