Xilinx SMPTE 2022-5/6 Product Manual page 49

Table B-1: Parameter Changes (Cont'd)
Version
v2.0/1 and v3.0
Include FEC Engine Include FEC
Port Changes
There are ports changes between older core versions (v2.0/2.1 and v3.0) compare to v4.0.
Table B-2 shows the details of changes involved.
Table B-2: Port Changes
v2.0/1 and v3.0
eth_rst
eth_clk
s_axis_aresetn
s_axis_tdata
s_axis_tkeep
s_axis_tvalid
s_axis_tuser
s_axis_tlast
m2_axi_*
rx[0-7]_rtp_pkt_recv
rx[0-7]_rtp_seq_num
rx[0-7]_rtp_vid_ts
rx[0-7]_rtp_ts
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
v4.0
Unchanged
Engine
Enable Seamless New to version v4.0. Refer
Switching Core for description.
Version
v4.0
rst27m
clk27m
pri_eth_rst
pri_eth_clk
sec_eth_rst
sec_eth_clk
pri_s_axis_tdata
pri_s_axis_tkeep
pri_s_axis_tvalid
pri_s_axis_tuser
pri_s_axis_tlast
sec_s_axis_tdata
sec_s_axis_tkeep
sec_s_axis_tvalid
sec_s_axis_tuser
sec_s_axis_tlast
rx[0-7]_pri_rtp_pkt_recv
rx[0-7]_pri_rtp_seq_num
rx[0-7]_pri_vid_ts
rx[0-7]_pri_rtp_ts
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Appendix B: Migrating and Upgrading
Note
Customizing and Generating the
Note
Newly added
Newly added
Renamed
Renamed
Newly added for seamless switching purpose
Newly added for seamless switching purpose
Removed
Renamed
Renamed
Renamed
Renamed
Renamed
Newly added for seamless switching purpose
Newly added for seamless switching purpose
Newly added for seamless switching purpose
Newly added for seamless switching purpose
Newly added for seamless switching purpose
Removed
Renamed
Renamed
Renamed
Renamed
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