Xilinx SMPTE 2022-5/6 Product Manual page 51

Table B-3: Port Changes as supporting SMPTE2022-7 Feature (Cont'd)
SMPTE 2022-5/6 TX v3.0 Ports
rxN_rtp_seq_num
rxN_rtp_vid_ts
rxN_rtp_rtp_ts
For minimum change migration, disable the Seamless Switching Feature and remap the
renamed ports accordingly by referring to
for more details on ports added in v4.0.
Register Setting
New registers to take note of which were added to support new functionality and features
as shown in below table
These are crucial registers that need to take note during migration.
Table B-4: Added Register in Register Map
Address General/
Offset Channel
0x028 General
0x034 General
0x038 General
0x11C Channel
0x12C Channel
0x130 Channel
1. Primary and Secondary registers are configured separately.
When configuring these new added register, refer to
Configurations in Chapter
For minimum change migration, disable the Seamless Switching and set the primary
registers accordingly. Refer to
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
Table
Table B-4.
Register Name
Bit Name
[31:0] network_path_differential
[31:0] fec_buf_base_addr
[31:0] fec_buf_pool_size
[31:0] playout_delay
[31:0] media_buf_base_addr
[15:0] media_pkt_buf_size
3.
Core Debug in Appendix C
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Appendix B: Migrating and Upgrading
SMPTE 2022-5/6 TX v4.0 Ports
rxN_pri_rtp_seq_num
rxN_sec_rtp_seq_num
rxN_pri_rtp_vid_ts
rxN_sec_rtp_vid_ts
rxN_pri_tp_rtp_ts
rxN_sec_rtp_rtp_ts
B-2. Refer Port Descriptions in Chapter 2
Register Description
Setting for maximum accepted delay
between 2 streams based on 27MHz
clock tick
DDR base address to store FEC packets
No. of Bytes of memory space to cater
for FEC buffer
Set time to SDI playout upon incoming
stream packet size lock. Value based on
27MHz clock ticks
Starting base address in the DDR to
store packets for each channels [make
sure doesn't overlap]
Maximum number of packets that can
hold in the DDR for each channel
Memory Requirement and Register
for register settings information.
51
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