Constraining The Core - Xilinx SMPTE 2022-5/6 Product Manual

User Parameters
Table 4-1 shows the relationship between the GUI fields in the Vivado IDE and the User
Parameters (which can be viewed in the Tcl console).
Table 4-1: GUI Parameter to User Parameter Relationship
GUI Parameter/Value
Number of SDI channels
include Forward Error Correction
Engine
Enable Seamless Switching
1. Parameter values are listed in the table where the GUI parameter value differs from the user parameter value. Such
values are shown in this table as indented below the associated parameter.
Output Generation
For details, see "Generating IP Output Products" in the Vivado Design Suite User Guide:
Designing with IP (UG896)

Constraining the Core

Required Constraints
Constraints required for the core are clock frequency constraints for the clock domains
described in Clocking in
domains are constrained with a max_delay constraint and use the datapathonly flag,
causing setup and hold checks to be ignored for signals that cross clock domains. These
constraints are provided in the XDC constraints file included with the core.
Device, Package, and Speed Grade Selections
There are no device, package or speed grade requirements for this core. This core has not
been characterized for use in low-power devices.
Clock Frequencies
See Maximum Frequencies in Chapter
Clock Management
See Clocking in Chapter
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
(1)
User Parameter/Value
C_CHANNELS
C_INCLUDE_FEC
C_INCLUDE_HITLESS
[Ref 6].
Chapter 3, Designing with the
2.
3.
www.xilinx.com
Chapter 4: Design Flow Steps
(1)
Default Value
1
FALSE
FALSE
Core. Paths between the clock
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