Port Descriptions - Xilinx SMPTE 2022-5/6 Product Manual

Port Descriptions

The core uses industry-standard control and data interfaces to connect to other system
components. The following sections describe the various interfaces available with the core.
Figure 2-2 shows an I/O Diagram of the core. The SDI_TX interface pins depend on the
number of channels configured through the Vivado Integrated Design Environment (IDE).
X-Ref Target - Figure 2-1 X-Ref Target - Figure 2-2
Figure 2-2: SMPTE 2022-5/6 Video over IP Receiver Core Interface
Common Interface
Table 2-4 summarizes the signals which are either shared by or are not part of the dedicated
SDI, AXI4-Stream, AXI4, or AXI4-Lite control interfaces.
Table 2-4: Common Interface Signals
Signal Name
rst27m
clk27m
sys_rst
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
Direction Width
In 1
In 1
In 1
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Description
27 Mhz domain reset
27 Mhz clock and is used for timekeeping
System domain reset.
Chapter 2: Product Specification
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