Xilinx SMPTE 2022-5/6 Product Manual page 38

5. Summing the each pool size,
AXI Memory Map Bandwidth Requirements
The memory bandwidth is calculated based on maximum input of 10Gbps per link to the
SMPTE 2022-5/6 RX including RTP and FEC packet regardless of Channel Number and SDI
Format.
The values on the table are based on worst case per port scenario.
Table 3-3: Receiver AXI-MM Port Bandwidth Consumption
M0_AXIMM WR
M0_AXIMM RD
M1_AXIMM WR
M1_AXIMM RD
Receiver Output Data Behavior
Figure 3-2 illustrates the receiver output data behavior.
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
Port
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Chapter 3: Designing with the Core
MaximumBandwidth (Gbps)
21.5
10.5
2.5
10.5
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