Chapter 3: Designing With The Core - Xilinx SMPTE 2022-5/6 Product Manual

Designing with the Core
The core is for broadcast applications that require bridging between SMPTE video
connectivity standards SD/HD/3G-SDI and 10Gb/s Ethernet. The core takes in Ethernet
packets encapsulated in accordance with SMPTE 2022-5/6 and maps them in uncompressed
SD/HD/3G-SDI streams to the SMPTE SD/HD/3G-SDI core. It receives Ethernet packets
through the AXI4-Stream interface from the 10 Gb/s Ethernet MAC. The core uses the AXI4
memory interface to transfer data between the core and external DDR memory. The register
control interface is compliant with AXI4-Lite interface. See SMPTE 2022-5/6 High Bit Rate
Media Transport Over IP Networks with Forward Error Correction (XAPP1199)
more information.
X-Ref Target - Figure 3-1
Figure 3-1: SMPTE 2022-5/6 Video over IP Receiver System Built with Other Xilinx IP Cores
1. Primary and Secondary ETH_AXIS exist only when seamless switching enabled.
There is an option to include Forward Error Correction engine in the SMPTE 2022-5/6 Video
Note:
over IP Receiver core. Adding this enables the receiver to recover IP packets lost to the network
transmission errors and hence ensure the quality of the uncompressed video. However, it will
increase the resource count in the FPGA as well as the usage of external memory. Enabling seamless
switching adds a redundancy protection link for packets lost to network transmission errors, which
also increases device resource count. Reset individual channel can be achieved by setting Bit 0 Low
in chan_en register (register offset 0x100). To reset the core, all active individual channels must be
reset and following by setting Bit 0 Low in reset register (register offset 0x004).
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
www.xilinx.com
Chapter 3
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