Revision History; Please Read: Important Legal Notices - Xilinx SMPTE 2022-5/6 Product Manual

Revision History

The following table shows the revision history for this document.
Date Version
10/01/2014
10/02/2013
03/20/2013
12/18/2012
10/16/2012
07/25/2012
04/24/2012

Please Read: Important Legal Notices

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS
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LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
• Revision number advanced to 4.0 with design architecture improvement.
4.0
• Updated the demonstration test bench.
• Updated GUI screens.
• Updated tables in
• Updated memory requirements for the core.
• Updated migrating and upgrading section.
3.0 • Added XDC and module level constraints to core.
• Added demonstration test bench.
• Changed all signals to lowercase.
• Revision number advanced to 3.0 to align with core version number
3.0
• Updated to core version 3.0 and Vivado Design Suite.
• Removed all material related to Virtex-6 devices, ISE Design Suite, CORE
Generator™ tools, and UCF.
• Updated GUIs.
• Updated Table 2-8 and 2-10.
2.1 • Updated to core version 2.1.
• Updated to ISE® design tools 14.4 and Vivado® Design Suite 2012.4.
• Updated Debug appendix.
• Updated design to support the latest SMPTE 2022-5/6 draft change.
• Removed MAC_LOW _ADDR, MAC_HIGH _ADDR, and IP_HOST_ADDR
registers.
• Updated screen captures in Chapter 4 and Chapter 6.
2.0.1 Updated with memory requirements for the core.
2.0 Updated to core version 2.0. Added Vivado Design Suite material and support
for Virtex-7 device.
Initial Xilinx release.
1.0
www.xilinx.com
Appendix D: Additional Resources and Legal Notices
Revision
Chapter 2, Product Specification.
57
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