Xilinx SMPTE 2022-5/6 Product Manual page 23

Table 2-10: AXI4-Lite Register Map (Cont'd)
Address (Hex) Register Name
0x008C match_dest_ip_addr
0x009C match_src_ip_addr
0x00AC match_src_port
0x00B0 match_dest_port
0x00B4 match_sel
0x00B8 link_reordered_ pkt_cnt
0x00BC link_stat_reset
0x00C0 link_valid_media_pkt_cnt
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
Default
Access Type
Value(HEX)
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R 0x00000000
R/W 0x00000000
R 0x00000000
Channel [Shared]
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Chapter 2: Product Specification
Description
Bit
Value
Range
Match Destination IP Address
31:0 32-bit IP host low
address
Match Source IP Address
31: 0 32-bit source IP
address
Match UDP Source Port
31:16 Reserved
15:0 16-bit UDP source port
address
Match UDP Destination Port
31:16 Reserved
15:0 16-bit UDP destination
port address used to
filter
Matching Selection
31:6 Reserved
5 To match SSRC
4 To match UDP dest port
3 To match UDP src port
2 To match Destination IP
1 To match Source IP
0 To match VLAN
Link Reordered Packet Count
31:0 Number of reordered
packets
Link Statistics Reset
31:2 Reserved
1 Reset valid_pkts_cnt
0 Reset reordered_
pkts_cnt
Link Valid Media Packet Count
31:0 Number of valid media
packets received in the
link per channel
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