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Xilinx SMPTE 2022-5/6 Product Manual

Xilinx SMPTE 2022-5/6 Product Manual

Video over ip receiver v4.0 logicore ip
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SMPTE 2022-5/6 Video
over IP Receiver v4.0
LogiCORE IP Product Guide
Vivado Design Suite
PG033 October 1, 2014

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Summary of Contents for Xilinx SMPTE 2022-5/6

  • Page 1 SMPTE 2022-5/6 Video over IP Receiver v4.0 LogiCORE IP Product Guide Vivado Design Suite PG033 October 1, 2014...

  • Page 2: Table Of Contents

    Upgrading in the Vivado Design Suite ..........48 LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com...
  • Page 3 Finding Help on Xilinx.com ........

  • Page 4: Ip Facts

    Provided with Core recovering IP packets lost due to network Design Files Encrypted HDL transmission errors and ensure the picture SMPTE 2022-5/6 High Bit Rate Media Transport quality of uncompressed, high bandwidth Example Over IP Networks with Forward Error Correction Design professional video is maintained.
  • Page 5 ° Link differential measure ° • Include or remove FEC engine or secondary link during compile time • AXI4-Stream data interfaces • AXI4-Lite control interface LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014 Product Specification...

  • Page 6: Chapter 1: Overview

    In real time systems, the latency is too great to request a retransmission. The ability of Xilinx FPGAs to bridge the broadcast and the communications industries by performing highly integrated real-time video interfaces help broadcasters reduce costs as well as reduce the overall time it takes to acquire, edit and produce content.

  • Page 7: Feature Summary

    IP license level is ignored at checkpoints. The test confirms a valid license exists. It does IMPORTANT: not check IP license level. If a Hardware Evaluation License is being used, the core will stop transmitting video after timeout. LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 8 Chapter 1: Overview License Type This Xilinx LogiCORE™ IP module is provided under the terms of the Xilinx Core License Agreement. The module is shipped as part of the Vivado Design Suite. For full access to all core functionalities in simulation and in hardware, you must IMPORTANT: purchase a license for the core.

  • Page 9: Chapter 2: Product Specification

    The maximum achievable clock frequency can vary. The maximum achievable clock frequency and all resource counts can be affected by other tool options, additional logic in the FPGA, using a different version of Xilinx tools and other factors. See the resource utilization tables for device family specific information.

  • Page 10: Resource Utilization

    RAMs RAMs DSP48E1s 7,698 6,546 2,531 8,380 10,585 8,665 3,643 11,341 13,434 10,103 4,756 14,258 16,305 10,702 5,637 16,702 19,145 12,140 6,501 19,299 22,016 13,418 7,516 21,975 LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 11 11,476 5,440 16,129 20,042 13,639 6,830 19,740 23,656 14,905 8,023 23,092 27,284 16,967 8,338 25,812 30,893 19,134 11,145 30,509 34,491 20,446 11,446 33,424 38,105 21,577 12,322 36,598 LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...

  • Page 12: Port Descriptions

    Vivado Integrated Design Environment (IDE). X-Ref Target - Figure 2-1 X-Ref Target - Figure 2-2 Figure 2-2: SMPTE 2022-5/6 Video over IP Receiver Core Interface Common Interface Table 2-4 summarizes the signals which are either shared by or are not part of the dedicated SDI, AXI4-Stream, AXI4, or AXI4-Lite control interfaces.
  • Page 13 Chapter 2: Product Specification Table 2-4: Common Interface Signals (Cont’d) Signal Name Direction Width Description sys_clk System clock interrupt Reserved soft_reset Core reset generated from specific control register bit LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 14 Read Address Channel Transaction ID m0_axi_araddr Read Address Channel Address m0_axi_arlen Read Address Channel Burst Length code m0_axi_arsize Read Address Channel Transfer Size code m0_axi_arburst Read Address Channel Burst Type LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 15 Write Data Channel Data Byte Strobes m1_axi_wlast Write Data Channel Last Data Beat m1_axi_wvalid Write Data Channel Valid m1_axi_wready Write Data Channel Ready m1_axi_bid Write Response Channel Transaction ID LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 16 Table 2-6: AXI4-Stream Interface Signals Signal Name Direction Width Description pri/sec_eth_rst Active-High reset from core pri/sec_eth_clk Recovered clock from XGMAC pri/sec_s_axis_tdata[63:0] AXI4-Stream Data from XGMAC pri/sec_s_axis_tkeep[7:0] AXI4-Stream Data Control from XGMAC LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 17 High, it indicates a bit rate of 1.485/1.001 Gb/s in HD-SDI mode and 2.97/1.001 Gb/s in 3G-SDI mode. 1. [0-7] is index that represent up to 8 channels support for SDI streams. LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback...
  • Page 18 MicroBlaze™. The core can be controlled through the AXI4-Lite interface using read and write transactions to the SMPTE 2022-5/6 Video over IP Receiver register space. The AXI4-Lite slave interface facilitates integrating the core into a processor system, or along with other video or AXI4-Lite compliant IP, connected through the AXI4-Lite interface to an AXI4-Lite master.
  • Page 19 AXI4-Lite Write Response Channel. Indicates results of the s_axi_bresp write transfer. AXI4-Lite Write Response Channel Response Valid. s_axi_bvalid Indicates response is valid. s_axi_awready AXI4-Lite Write Address Channel Write Address Ready. LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...

  • Page 20: Register Space

    Chapter 2: Product Specification Register Space The SMPTE 2022-5/6 Video over IP Receiver register space is partitioned to General and Channel specific registers. See the SMPTE 2022-5/6 reference design for more information on register usage. Table 2-10: AXI4-Lite Register Map...
  • Page 21 31:0 Number of errored packets received in the primary stream 0x0048 sec_err_pkt_cnt 0x00000000 Secondary Errored Packet Count 31:0 Number of errored packets received in the secondary stream LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 22 VLAN filtering 0 - Filter stream without VLAN, 1 - Filter stream with VLAN having tag info in bit 15:0 30:16 Reserved 15:0 16-bit VLAN tag info LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 23 Reset valid_pkts_cnt Reset reordered_ pkts_cnt 0x00C0 link_valid_media_pkt_cnt 0x00000000 Link Valid Media Packet Count 31:0 Number of valid media packets received in the link per channel Channel [Shared] LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 24 1 - SDI frame out of sync. Packet count for the SDI frame does not match the video format Packet size locked indicator 0 - Not locked 1 - Locked LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 25 10-bit L value from the received header 0x0128 seamless_protect 0x00000000 Seamless Protect Seamless status 0- not protected. 1 - protected 30:0 RTP timestamp difference between incoming primary and secondary stream packets LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 26 1 - indicate that media buffer overflowed 0x0158 unrec_ pkt_cnt 0x00000000 Unrecoverable Packet Count 31:0 Number of unrecoverable packets 0x0160 oor_ pkt_cnt 0x00000000 Out-Of-Range Packet Count 31:0 Number of out-of-range packets LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 27 NETWORK_PATH_DIFFERENTIAL (0x028) Register Set the maximum delay between primary and secondary link for the core to operate in seamless switching mode. The value is based on a 27MHz clock tick. LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 28 GEN_STAT_RESET (0x054) Register A High to Bit 5 resets secondary discarded packet counter (register 0x050). A High to Bit 4 resets primary discarded packet counter (register 0x04C). LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 29 Match if VLAN TAG ID = Bit [15:0] of Not Match Match VLAN MATCH_DEST_IP_ADDR (0x08C) Register This parameter is used in filtering the packets for the channel. Configure Bit 31-0 for Destination IP address matching. LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 30 Register 0x0BC, bit 0 resets the counter. LINK_STAT_RESET (0x0BC) Register • A High to Bit 1 resets link valid media packet counter (register 0x0C0). LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 31 The channel needs to be reset to ensure proper operation. VID_SRC_FMT (0x118) Register • Bit 31-28 refers to MAP parameter in SMPTE 2022-6 specification LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 32 This register sets the maximum number of media packets to be stored in the DDR for the channel. It has a limitation of 16 bits (Bit 15-0) and has to be in written in the value of (2^n-1). LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback...
  • Page 33 (NETWORK_PATH_DIFFERRENTIAL + PLAYOUT_DELAY). The incoming packet is discarded and not processed further. This counter is per channel and register 0x10C, bit 5 resets it. Note that massive out-of-range packets may cause the core to stop working. LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback...

  • Page 34: Chapter 3: Designing With The Core

    X-Ref Target - Figure 3-1 Figure 3-1: SMPTE 2022-5/6 Video over IP Receiver System Built with Other Xilinx IP Cores 1. Primary and Secondary ETH_AXIS exist only when seamless switching enabled. There is an option to include Forward Error Correction engine in the SMPTE 2022-5/6 Video Note: over IP Receiver core.

  • Page 35: Clocking

    Secondary Ethernet clock domain at 156.25 MHz • AXI4-Lite clock domain recommended at 100 MHz Resets The SMPTE 2022-5/6 Video over IP Receiver core has five (or six when Seamless Switching enabled) main resets: • Primary Ethernet link reset, pri_eth_rst •...

  • Page 36: Memory Requirement And Register Configurations

    Then compute packets buffered for FEC correction; Packet margin is set to 64 as to give some time for FEC recovery process. The summed packet buffered is computed as; LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 37 4. FEC Buffer Base Address can be set after the media buffer allocation by, Finally set FEC Buffer Pool Size (in bold) by computing: For each channel, LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 38 AXI Memory Map Bandwidth Requirements The memory bandwidth is calculated based on maximum input of 10Gbps per link to the SMPTE 2022-5/6 RX including RTP and FEC packet regardless of Channel Number and SDI Format. The values on the table are based on worst case per port scenario.
  • Page 39 Chapter 3: Designing with the Core X-Ref Target - Figure 3-2 Figure 3-2: Receiver Output Data Behavior LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...

  • Page 40: Chapter 4: Design Flow Steps

    The core is configured to meet the developer's specific needs before instantiation through the Vivado IDE. This section provides a quick reference to parameters that can be configured at generation time. LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback...
  • Page 41 Error Correction engine is generated in the core. The core is capable of recovering IP packets lost to network transmission errors. • Enable Seamless Switching: When checked, the core is generated with Secondary AXIS Ethernet Link to support seamless operation. LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...

  • Page 42: Constraining The Core

    There are no device, package or speed grade requirements for this core. This core has not been characterized for use in low-power devices. Clock Frequencies Maximum Frequencies in Chapter Clock Management Clocking in Chapter LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...

  • Page 43: Simulation

    Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref Synthesis and Implementation For details about synthesis and implementation, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...

  • Page 44: Chapter 5: Test Bench

    SDI stream data checker module on the ® Vivado IDE console. Demonstration Test Bench Architecture Figure 5-1 shows the test bench architecture. LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 45 Assert error if there is any data mismatched. Also detects SOF on the input and output streams to signal successful data transmission and reception by the TX and RX core respectively. LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback...
  • Page 46 SMPTE TX Simulation model which is an encrypted version of the VOIP Transceiver core in a loopback mode in the test bench. You cannot view the encrypted model. LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...

  • Page 47: Appendix A: Verification, Compliance, And Interoperability

    Appendix A Verification, Compliance, and Interoperability The SMPTE 2022-5/6 Video over IP Receiver core has been validated using the Xilinx Kintex®-7 FPGA Connectivity Kit. See SMPTE 2022-5/6 High Bit Rate Media Transport Over IP Networks with Forward Error Corrections (XAPP1199) [Ref 1] for more information.

  • Page 48: Appendix B: Migrating And Upgrading

    Suite Migration Guide (UG911) [Ref Upgrading in the Vivado Design Suite SMPTE 2022-5/6 Video Over IP Receiver version 4.0 had the following changes implemented, and may not be compatible with previous versions cores (v2.0, v2.1 and v3.0). Parameter Changes Table B-1 shows the details of changes involved.
  • Page 49 Newly added for seamless switching purpose sec_s_axis_tlast Newly added for seamless switching purpose m2_axi_* Removed rx[0-7]_rtp_pkt_recv rx[0-7]_pri_rtp_pkt_recv Renamed rx[0-7]_rtp_seq_num rx[0-7]_pri_rtp_seq_num Renamed rx[0-7]_rtp_vid_ts rx[0-7]_pri_vid_ts Renamed rx[0-7]_rtp_ts rx[0-7]_pri_rtp_ts Renamed LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...
  • Page 50 SMPTE 2022-5/6 RX Migration from v3.0 to v4.0 Port Changes In SMPTE 2022-5/6 RX v4.0, a new feature was added which supports SMPTE 2022-7, where the receiver core receives two identical/seamless AXI-Streams (Primary and Secondary) with different header as configured by the user. The port changes related to the new feature are...
  • Page 51 Configurations in Chapter For minimum change migration, disable the Seamless Switching and set the primary registers accordingly. Refer to Core Debug in Appendix C for register settings information. LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...

  • Page 52: Appendix C: Debugging

    Answer Records Answer Records include information about commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a Xilinx product. Answer Records are created and maintained daily ensuring that users have access to the most accurate information available.

  • Page 53: Vivado Lab Tools

    LogiCORE™ IP product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that are not defined in the documentation, if customized beyond that allowed in the product documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.

  • Page 54: Interface Debug

    Check that the aclk inputs are connected and toggling. • Check that the AXI4-Stream waveforms are being followed. • Check core configuration. • Add appropriate core specific checks. LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...

  • Page 55: Core Debug

    [31:9] of network_path_differential (0x028) and bits [31:9] of playout_delay (0x11C) registers. 6. Ensure that the curr_pkts_buffered (0x140) is not greater than the media_pkt_buf_size (0x130) register. LogiCORE IP SMPTE 2022-5/6 RX v4.0 www.xilinx.com Send Feedback PG033 October 1, 2014...

  • Page 56: Appendix D: Additional Resources And Legal Notices

    Glossary. References These documents provide supplemental material useful with this product guide. 1. SMPTE 2022-5/6 High Bit Rate Media Transport Over IP Networks with Forward Error Correction (XAPP1199) 2. AXI Design Reference Guide (UG761) 3. LogiCORE IP AXI Interconnect Product Guide (PG059) 4.

  • Page 57: Revision History

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
  • Page 58 Xilinx's Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

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