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Clocking
The core has six clock domains:
•
27MHz clock domain
•
SDI video clock domain
•
System clock domain recommended running at 200 MHz
•
Primary Ethernet clock domain at 156.25 MHz
•
Secondary Ethernet clock domain at 156.25 MHz
•
AXI4-Lite clock domain recommended at 100 MHz
Resets
The SMPTE 2022-5/6 Video over IP Receiver core has five (or six when Seamless Switching
enabled) main resets:
•
Primary Ethernet link reset, pri_eth_rst
•
Secondary Ethernet link reset, sec_eth_rst
•
System domain reset, sys_rst
•
27Mhz domain reset, rst27m
•
SDI domain reset, tx<port_num>_rst
•
AXI4-Lite domain reset, s_axi_aresetn
Reset Requirements
•
The resets must be synchronous to their individual clock domains.
•
A minimum of 16 clocks assertion is recommended.
•
The ordering of reset de-assertion is not important except the pri_eth_rst and
sec_eth_rst have to be the last.
Refer to SMPTE 2022-5/6 High Bit Rate Media Transport Over IP Networks with Forward Error
Correction (XAPP1199)
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
[Ref
1].
www.xilinx.com
Chapter 3: Designing with the Core
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