Xilinx SMPTE 2022-5/6 Product Manual page 28

FEC_BUF_BASE_ADDR (0x034) Register
This sets the base address of the memory allocated in the DDR to store the FEC packets for
recovery.
FEC_BUF_POOL_SIZE (0x038) Register
This register allocates the memory buffer size in the DDR for FEC packets storage. The value
is in terms of bytes.
PRI_RECV_PKT_CNT (0x03C) Register
Primary received packet counter increments when a packet is filtered into the channels in
the primary link. Register 0x054, bit 0 resets it.
SEC_RECV_PKT_CNT (0x040) Register
Secondary received packet counter increments when a packet is filtered into the channels in
the secondary link. Register 0x054, bit 1 resets it.
PRI_ERR_PKT_CNT (0x044) Register
Primary error packet counter increments when a packet is identified as bad frame from the
MAC core in the primary link. Register 0x054, bit 2 resets it.
SEC_ERR_PKT_CNT (0x048) Register
Secondary error packet counter increments when a packet is identified as bad frame from
the MAC core in the secondary link. Register 0x054, bit 3 resets it.
PRI_DISCARD_PKT_CNT (0x04C) Register
Primary discard packet counter increments when a packet is not accepted for any of the
channels in the primary link. Register 0x054, bit 4 resets it.
SEC_DISCARD_PKT_CNT (0x050) Register
Secondary discard packet counter increments when a packet is not accepted for any of the
channels in the secondary link. Register 0x054, bit 5 resets it.
GEN_STAT_RESET (0x054) Register
A High to Bit 5 resets secondary discarded packet counter (register 0x050).
A High to Bit 4 resets primary discarded packet counter (register 0x04C).
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
www.xilinx.com
Chapter 2: Product Specification
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