Xilinx SMPTE 2022-5/6 Product Manual page 32

• Bit 27-20 refers to FRAME parameter in SMPTE 2022-6 specification
• Bit 19-12 refers to FRATE parameter in SMPTE 2022-6 specification
• Bit 11-8 refers to SAMPLE parameter in SMPTE 2022-6 specification
PLAYOUT_DELAY (0x11C) Register
Sets the wait time before the buffered SDI data is ready for play out after packet size lock
(register 0x120, bit 0) and marker bit packet detected. The value is based on 27MHz clock
tick.
FEC_PARAM (0x124) Register
Read-only status on the FEC parameters detected by the channel.
Bit 20 is High upon first detection of FEC packet for the channel. Detection will not start
before register 0x120, bit 0 is High.
When Bit 20 is High:
• Bit 9-0 shows the L value of FEC matrix.
• Bit 19-10 shows the D value of FEC matrix.
• Bit 21 shows the FEC protection level. Bit 21 is Low for Level A stream and High for
Level B.
SEAMLESS_PROTECT (0x128) Register
Bit 30-0 samples the RTP timestamp difference between incoming packets from the primary
and secondary links of a channel.
Bit 31 indicates whether the channel is under seamless protection. The channel is
considered protected when the RTP timestamps of the media packets from both primary
and secondary links fall within the range defined by NETWORK_PATH_DIFFERRENTIAL and
PLAYOUT_DELAY.
MEDIA_PKT_BASE_ADDR (0x12C) Register
This register sets the base address of the memory buffer allocated in the DDR to store the
media packets for FEC recovery and play out.
MEDIA_PKT_BUF_SIZE (0x130) Register
This register sets the maximum number of media packets to be stored in the DDR for the
channel. It has a limitation of 16 bits (Bit 15-0) and has to be in written in the value of
(2^n-1).
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
www.xilinx.com
Chapter 2: Product Specification
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