Memory Requirement And Register Configurations - Xilinx SMPTE 2022-5/6 Product Manual

Memory Requirement and Register Configurations

Base Address, Packet Buffer and Playout Delay Registers
Configurations
Follow the computation below to get the configuration values to obtain the Media Packet
Buffer Size and play out delay (in bold). These configuration values must be set before
enabling the channel.
*notes, all computation below are per-channel basis.
SMPTE 2022-567 Computation is based with this SDI rate:
Table 3-1: SDI Rate
SDI Format
SD
HD
3G
*SMPTE 2022-567 Payload Size: 1376 Bytes
Then compute for packet buffered for packet delay;
Then compute for packet buffered for packet delay;
*
Then compute packets buffered for FEC correction;
Packet margin is set to 64 as to give some time for FEC recovery process.
The summed packet buffered is computed as;
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
Maximum SDI Bitrate (Mbps)
270
1485
2970
is set when Seamless Switching is being used.
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