Xilinx SMPTE 2022-5/6 Product Manual page 18

Ethernet Packets Received Interface
See the SMPTE 2022-5/6 reference design for more information.
Table 2-8: Ethernet Packets Received Interface Signals
(1)
Signal Name
rx[0-7]_pri/sec_rtp_pkt_recv
rx[0-7]_pri/sec_rtp_seq_num
rx[0-7]_rtp_pkt_buffered
rx[0-7]_rtp_pkt_transmit
rx[0-7]_pkt_lock
rx[0-7]_pri/sec_vid_ts
rx[0-7]_pri/sec_rtp_ts
rx[0-7]_playout_ready
1. [0-7] is index that represent up to 8 channels support for SDI streams.
AXI4-Lite Control Interface
The AXI4-Lite interface allows you to dynamically control parameters within the core. Core
configuration can be accomplished using an embedded ARM® or soft system processor
such as MicroBlaze™.
The core can be controlled through the AXI4-Lite interface using read and write
transactions to the SMPTE 2022-5/6 Video over IP Receiver register space.
The AXI4-Lite slave interface facilitates integrating the core into a processor system, or
along with other video or AXI4-Lite compliant IP, connected through the AXI4-Lite interface
to an AXI4-Lite master. See the LogiCORE IP AXI Interconnect Product Guide (PG059)
for more information.
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
Direction Width Description
Pulse indicating receiving of RTP packet from
Out 1 primary/secondary link. (synchronous to
pri/sec_eth_clk)
Sequence number of RTP packet received from
Out 16 primary/secondary link. (Synchronous to
pri/sec_eth_clk)
Amount of RTP packets buffered. (Synchronous to
Out 16
pri_eth_clk)
Pulse indicating consumption of RTP packet for
Out 1
SDI output. (Synchronous to pri_eth_clk)
Indication of channel locking to certain payload.
Out 1
(Synchronous to pri_eth_clk)
Video timestamp of the RTP packet received from
Out 32 primary/secondary link. (Synchronous to
pri/sec_eth_clk)
RTP timestamp of the RTP packet received from
Out 32 primary/secondary link. (Synchronous to
pri/sec_eth_clk)
Indication of channel ready for playing out the TS
Out 1
data. (Synchronous to pri_eth_clk)
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