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Xilinx I2S Product Manual

Xilinx I2S Product Manual

Logicore ip, vivado design suite
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I2S Transmitter and I2S
Receiver v1.0
LogiCORE IP Product Guide
Vivado Design Suite
PG308 (v1.0) April 4, 2018

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Summary of Contents for Xilinx I2S

  • Page 1 I2S Transmitter and I2S Receiver v1.0 LogiCORE IP Product Guide Vivado Design Suite PG308 (v1.0) April 4, 2018...

  • Page 2: Table Of Contents

    Licensing and Ordering......................6 Chapter 3: Product Specification ................8 Performance..........................9 Resource Use..........................9 Port Descriptions........................10 I2S Transmitter Register Space....................11 I2S Receiver Register Space..................... 16 Chapter 4: Designing with the Core ..............22 General Design Guidelines.......................23 Clocking............................24 Resets............................24...
  • Page 3 Appendix B: Additional Resources and Legal Notices ......38 Xilinx Resources.........................38 Documentation Navigator and Design Hubs.................38 References..........................39 Training Resources........................39 Revision History......................... 39 Please Read: Important Legal Notices................... 40 PG308 (v1.0) April 4, 2018 www.xilinx.com [placeholder text] Send Feedback I2S Transmitter and I2S Receiver...

  • Page 4: Chapter 1: Ip Facts

    Chapter 1 IP Facts ® The Xilinx LogiCORE™ IP I2S Transmitter and LogiCORE™ Receiver cores are soft Xilinx IP cores for use with the Xilinx Vivado ® Design Suite, which makes it easy to implement inter-IC-sound (I2S) interface used to connect audio devices for transmitting and receiving PCM audio.
  • Page 5 <release>/data/embeddedsw/doc/xilinx_drivers.htm). Linux OS and driver support information is available from the Xilinx Wiki page. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide. PG308 (v1.0) April 4, 2018 www.xilinx.com [placeholder text] Send Feedback I2S Transmitter and I2S Receiver...

  • Page 6: Chapter 2: Overview

    Chapter 2 Overview The I2S Tramsmitter and I2S Receiver cores provide an easy way to interface the I2S based audio DAC/ADC. These IPs require minimal register programming and also support any audio sampling rates. These IPs can be used along side HDMI, DisplayPort, and SDI for complete audio video solution.
  • Page 7 Vivado ® Design Suite; Purchase means that you have to purchase a license to use the core. For more information about this core, visit the I2S Tramsmitter and I2S Receiver product web page ® Information about other Xilinx LogiCORE™...

  • Page 8: Chapter 3: Product Specification

    Chapter 3: Product Specification Chapter 3 Product Specification The I2S Tramsmitter and I2S Receiver IPs can be used to develop audio solution using I2S ADC/ DACs. These IPs support any sampling rate and are very easy to configure with minimal register programming.

  • Page 9: Performance

    For full details about performance and resource use, visit the Performance and Resource Use web page for transmitter and Performance and Resource Use web page for receiver. PG308 (v1.0) April 4, 2018 www.xilinx.com [placeholder text] Send Feedback I2S Transmitter and I2S Receiver...

  • Page 10: Port Descriptions

    Input SCK Clock. Available when core is configured as Slave sdata_0_out SDATA0 I2S Serial Data out sdata_1_out SDATA1 I2S Serial Data out. Available when number of audio channels is > 2 sdata_2_out SDATA2 I2S Serial Data out. Available when number of audio channels is > 4 sdata_3_out SDATA3 I2S Serial Data out.

  • Page 11: I2S Transmitter Register Space

    Input SCK Clock. Available when core is configured as Slave sdata_0_in SDATA0 I2S Serial Data In sdata_1_in SDATA1 I2S Serial Data In. Available when number of audio channels is > 2 sdata_2_in SDATA2 I2S Serial Data In. Available when number of audio channels is > 4 sdata_3_in SDATA3 I2S Serial Data In.
  • Page 12 Number of Audio Channels: Indicates the number of audio channels supported. Valid values are 2, 4, 6 and 8 Reserved Is I2S Master: Indicates if the core has been generated as an I2S Master or Slave. 1 = I2S Master PG308 (v1.0) April 4, 2018 www.xilinx.com...
  • Page 13 AES Block Sync Error: This bit is set when synchronization with the start of an AES block has been lost. This occurs if the incoming audio our AXIS does violates the guidelines. Write a ‘1’ to clear this flag. PG308 (v1.0) April 4, 2018 www.xilinx.com [placeholder text] Send Feedback I2S Transmitter and I2S Receiver...
  • Page 14 This registers is used to set the divider value to generate the SCLK. Typically SCLK = 2*24*Fs. Where 24 is I2S data width (this could be 16 also) and Fs is the audio sampling rate. Table 8: Transmitter I2S Timing Control (0x20)
  • Page 15 The IP provides a mechanism to route the audio channels onto any I2S output. For example, audio received on channels 2/3 can be routed to output on any of the four I2S ports. Similarly audio received on channels 0/1 can be routed to all of the four I2S ports.

  • Page 16: I2S Receiver Register Space

    Channel Mux Value: Specify a value to Multiplex the audio channel output. 0x0 : Output on I2S channel 3 is disabled 0x1 : I2S channel 3 outputs the audio received on channel 0 /1 0x2 : I2S channel 3 outputs the audio received on channel 2 /3...
  • Page 17 Default Access Description Value Type 31:17 RSVD I2S Data Width: Indicates the I2S Data width of the core 1 = 24 bit 0 = 16 bit 15:12 RSVD 11:8 Number of Audio Channels: Indicates the number of audio channels supported.
  • Page 18 Description Value Type RSVD Is I2S Master: Indicates if the core has been generated as an I2S Master or Slave. 1 = I2S Master Control Register (0x08) This register provides capability to enable/disable the core. Table 17: Receiver Control Register (0×08)
  • Page 19 The IP provides a mechanism to route the audio from any I2S input. For example, audio received on I2S Channel 0 can be routed to any of the 8 audio channels. Similarly audio received on one I2S channel can be routed to all of the eight audio channels.
  • Page 20 The IP provides a mechanism to route the audio from any I2S input. For example, audio received on I2S Channel 0 can be routed to any of the 8 audio channels. Similarly audio received on one I2S channel can be routed to all of the 8 audio channels.
  • Page 21 Channel Mux Value: Specify a value to Multiplex the audio channel output. 0x0 : disabled 0x1 : Audio received on I2S channel 3 is routed as audio channel 0 /1 0x2 : Audio received on I2S channel 3 is routed as audio channel 2 /3...

  • Page 22: Chapter 4: Designing With The Core

    Chapter 4: Designing with the Core Chapter 4 Designing with the Core The I2S TX and RX IPs can be used in systems to send and receive I2S audio. A typical use case is as shown below. System Using TX RX...

  • Page 23: General Design Guidelines

    General Design Guidelines Use the Example Design Each instance of the I2S Tramsmitter and I2S Receiver core created by the Vivado design tool is delivered with an example design that can be implemented in a device and then simulated. This design can be used as a starting point for your own design or can be used to sanity-check your application in the event of difficulty.

  • Page 24: Clocking

    AXIS domain. After a reset, it is advisable to disable and enable the IP for a clean recovery. Programmimg Sequence The I2S Transmitter can be setup using the following programming sequence: 1. Setup the Channel Mux registers, if required. Note It is not recommended to change this value at runtime.

  • Page 25: Interrupts

    (TVLD) and ready (TRDY) signals are asserted. The I2S Receiver sends out adjacent channels in sequential order (CH0, CH1, etc). Usually, the I2S Transmitter also expects the channels in sequential order. If the channel data is not in order, then the I2S Transmitter would assert underflow or block sync error.
  • Page 26 Table 27: Audio Axis Interface Patterns Bits [3:0] Description 0001 Start of Audio Block/Channel 0 Audio sample 0010 Channel 0/2/4/6 Audio data 0011 Channel 1/3/5/7 Audio data PG308 (v1.0) April 4, 2018 www.xilinx.com [placeholder text] Send Feedback I2S Transmitter and I2S Receiver...

  • Page 27: Chapter 5: Design Flow Steps

    2. Open the IP catalog and navigate to the taxonomies. 3. Double-click on either I2S Receiver or Transmitter to bring up the customize IP window. For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).
  • Page 28 Chapter 5: Design Flow Steps I2S Receiver Customize IP I2S Receiver Configuration Tab Figure 5: PG308 (v1.0) April 4, 2018 www.xilinx.com [placeholder text] Send Feedback I2S Transmitter and I2S Receiver...
  • Page 29 • FIFO Depth : Specify the depth of the FIFO. Allowed values are 64, 128, 256, 512 and 1024. In case of I2S Transmitter, the data is output on I2S interface only after the FIFO if half filled. • Enable FIFO Data Count: Select this option to enable the IP to output the FIFO Read data count.

  • Page 30: Constraining The Core

    It is advisable to have the Audio Clock generated from a stable source for minimal jitter. If the jitter is of low importance, a MMCM can be used to generate the Audio clock. PG308 (v1.0) April 4, 2018 www.xilinx.com [placeholder text] Send Feedback I2S Transmitter and I2S Receiver...

  • Page 31: Simulation

    Vivado Design Suite User Guide: Logic Simulation (UG900). Synthesis and Implementation For details about synthesis and implementation, see the Vivado Design Suite User Guide: Designing with IP (UG896). PG308 (v1.0) April 4, 2018 www.xilinx.com [placeholder text] Send Feedback I2S Transmitter and I2S Receiver...

  • Page 32: Chapter 6: Example Design

    AXI4-Lite clock, and the AXI4-Stream clock. The example design is held in reset until the MMCM is locked. • Axi Traffic Generator (ATG): The ATGs are used to program the I2S IPs. The ATGs start the configuration process as soon as the MMCM is locked.

  • Page 33: Implementing The Example Design

    If the test fails, the following message displays: Test Failed!!! If the test passes, the following message displays: Test Completed Successfully If the test hangs, the following message displays: Test Failed!! Test Timed Out PG308 (v1.0) April 4, 2018 www.xilinx.com [placeholder text] Send Feedback I2S Transmitter and I2S Receiver...

  • Page 34: Test Bench For Example Design

    The above figure shows the test bench for example design. The top-level test bench feeds a clock input, AXIS data to the exdes. The TB also checks the received AXIS data • AXIS Data Generator: This module generates the AXIS Audio traffic and feeds the I2S Transmitter.

  • Page 35: Appendix A: Debugging

    Appendix A Debugging This appendix includes details about resources available on the Xilinx Support website and debugging tools. If the IP requires a license key, the key must be verified. The Vivado ® design tools have several license checkpoints for gating licensed IP through the flow. If the license check succeeds, the IP can continue generation.
  • Page 36 Answer Records include information about commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a Xilinx product. Answer Records are created and maintained daily ensuring that users have access to the most accurate information available.

  • Page 37: Hardware Debug

    Masters. The I2S IPs only support 16 or 24 bit I2S mode only. 2. Audio has a lot of noise: Ensure that DAC/ADC/CODEC are configured for the same data width as the I2S IPs. Also ensure that the MCLK supplied to the DAC/ADC/CODEC is same as the one supplied to I2S IPs.

  • Page 38: Appendix B: Additional Resources And Legal Notices

    Hubs Xilinx ® Documentation Navigator provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open the Xilinx Documentation Navigator (DocNav): • From the Vivado ® IDE, select Help → Documentation and Tutorials.

  • Page 39: References

    Vivado Design Suite Tool Flow Revision History The following table shows the revision history for this document. Section Revision Summary 04/04/2018 v1.0 Initial Xilinx release. PG308 (v1.0) April 4, 2018 www.xilinx.com [placeholder text] Send Feedback I2S Transmitter and I2S Receiver...

  • Page 40: Please Read: Important Legal Notices

    IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for...

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