Simulation; Synthesis And Implementation - Xilinx SMPTE 2022-5/6 Product Manual

Clock Placement
There are no specific clock placement requirements for this core.
Banking
There are no specific Banking rules for this core.
Transceiver Placement
There are no transceiver placement requirements for this core.
I/O Standard and Placement
There are no specific I/O standards and placement requirements for this core.

Simulation

For comprehensive information about Vivado simulation components, as well as
information about using supported third-party tools, see the Vivado Design Suite User
Guide: Logic Simulation (UG900)

Synthesis and Implementation

For details about synthesis and implementation, see the Vivado Design Suite User Guide:
Designing with IP (UG896)
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
[Ref 7].
[Ref 6].
www.xilinx.com
Chapter 4: Design Flow Steps
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