Xilinx SMPTE 2022-5/6 Product Manual page 21

Table 2-10: AXI4-Lite Register Map (Cont'd)
Address (Hex) Register Name
0x0024 version
0x0028 network_path_differential
0x0034 fec_buf_base_addr
0x0038 fec_buf_pool_size
0x003C pri_recv_pkt_cnt
0x0040 sec_recv_pkt_cnt
0x0044 pri_err_pkt_cnt
0x0048 sec_err_pkt_cnt
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
Default
Access Type
Value(HEX)
R 0x04000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R 0x00000000
R 0x00000000
R 0x00000000
R 0x00000000
www.xilinx.com
Chapter 2: Product Specification
Description
Bit
Value
Range
Version
31:24 Version major
23:16 Version minor
15:12 Version revision
11:8 Patch ID
7:0 Revision number
Network Path Differential
31:0 max accepted delay
between 2 streams in
hitless, value based on
27MHz clock ticks
FEC Buffer Base Address
31:0 Base address on where
the buffer begins in the
DDR
FEC Buffer Pool Size
31:0 No. of Bytes of memory
space to cater for FEC
buffer
Primary Received Packet Count
31:0 Number of packets
received in the primary
stream
Secondary Received Packet
Count
31:0 Number of packets
received in the
secondary stream
Primary Errored Packet Count
31:0 Number of errored
packets received in the
primary stream
Secondary Errored Packet Count
31:0 Number of errored
packets received in the
secondary stream
Send Feedback
21