Interface Debug - Xilinx SMPTE 2022-5/6 Product Manual

The Vivado lab tools logic analyzer is used to interact with the logic debug LogiCORE IP
cores, including:
• ILA 2.0 (and later versions)
• VIO 2.0 (and later versions)
See Vivado Design Suite User Guide: Programming and Debugging (UG908)

Interface Debug

AXI4-Lite Interfaces
Read from a register that does not have all 0s as a default to verify that the interface is
functional. Output s_axi_arready asserts when the read address is valid, and output
s_axi_rvalid asserts when the read data/response is valid. If the interface is
unresponsive, ensure that the following conditions are met:
• The s_axi_aclk and aclk inputs are connected and toggling.
• The interface is not being held in reset, and s_axi_areset is an active-Low reset.
• The interface is enabled, and s_axi_aclken is active-High (if used).
• The main core clocks are toggling and that the enables are also asserted.
• If the simulation has been run, verify in simulation and/or a Vivado Lab Tools capture
that the waveform is correct for accessing the AXI4-Lite interface.
AXI4-Stream Interfaces
If data is not being transmitted or received, check the following conditions:
• If transmit <interface_name>_tready is stuck Low following the
<interface_name>_tvalid input being asserted, the core cannot send data.
• If the receive <interface_name>_tvalid is stuck Low, the core is not receiving
data.
• Check that the aclk inputs are connected and toggling.
• Check that the AXI4-Stream waveforms are being followed.
• Check core configuration.
• Add appropriate core specific checks.
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
www.xilinx.com
Appendix C: Debugging
[Ref 10].
54
Send Feedback