Xilinx SMPTE 2022-5/6 Product Manual page 14

AXI4 Memory Master Interface
The core uses an AXI4 interface to connect to the AXI4 interconnect. The AXI4 Interconnect
provides the access to the external memory through the AXI Double Data Rate (DDR)
controller. See the LogiCORE IP AXI Interconnect Product Guide (PG059)
information.
Table 2-5: AXI4 Memory Interface Signals
Signal Name
m0_axi_awid
m0_axi_awaddr
m0_axi_awlen
m0_axi_awsize
m0_axi_awburst
m0_axi_awlock
m0_axi_awcache
m0_axi_awprot
m0_axi_awqos
m0_axi_awvalid
m0_axi_awready
m0_axi_wdata
m0_axi_wstrb
m0_axi_wlast
m0_axi_wvalid
m0_axi_wready
m0_axi_bid
m0_axi_bresp
m0_axi_bvalid
m0_axi_bready
m0_axi_arid
m0_axi_araddr
m0_axi_arlen
m0_axi_arsize
m0_axi_arburst
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
Direction Width
Out 1 Write Address Channel Transaction ID
Out 32
Out 8
Out 3 Write Address Channel Transfer Size code
Out 2 Write Address Channel Burst Type
Out 2 Write Address Channel Atomic Access Type
Out 4 Write Address Channel Cache Characteristics
Out 3 Write Address Channel Protection Bits
Out 4 Write Address Channel Quality of Service
Out 1 Write Address Channel Valid
In 1
Out 256 Write Data Channel Data
Out 32 Write Data Channel Data Byte Strobes
Out 1 Write Data Channel Last Data Beat
Out 1 Write Data Channel Valid
In 1 Write Data Channel Ready
In 1 Write Response Channel Transaction ID
In 2 Write Response Channel Response Code
In 1 Write Response Channel Valid
Out 1 Write Response Channel Ready
Out 1
Out 32
Out 8 Read Address Channel Burst Length code
Out 3
Out 2 Read Address Channel Burst Type
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Chapter 2: Product Specification
Description
Write Address Channel Address
Write Address Channel Burst Length code
Write Address Channel Ready
Read Address Channel Transaction ID
Read Address Channel Address
Read Address Channel Transfer Size code
[Ref 3] for more
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