CONTROL (0x000) Register
Bit 1 of the CONTROL register is a write-done semaphore for the host processor, which
facilitates committing all user register updates in the channel space simultaneously. One set
of registers (the processor registers) is directly accessed by the processor interface, while
the other set (the active set) is actively used by the core. New values written to the
processor registers are copied over to the active set if and only if the register update bit is
set. Setting the bit to 0 before updating multiple registers and then setting the bit to 1
when updates are completed ensures all channel space registers are updated
simultaneously.
RESET (0x004) Register
Bit 0 is software reset. When High, the configuration registers are held at reset state. At the
same time, the soft_reset signal at the core interface is held High.
CHANNEL_ACCESS (0x00C) Register
Set the channel to access. All the primary link and secondary link channels share the same
set of register address in the channel space. To access secondary link channels, set bit 31 to
1. Only 0x084 - 0x0C0 registers are available for secondary link. Bit 7-0 represent the
channel number in standard binary count.
SYS_CFG (0x020) Register
System configuration of the core.
Bit 31 High indicates seamless switching support.
Bit 30 High indicates FEC engine is included.
Bit 7-0 gives the number of channels available to use.
VERSION (0x024) Register
Bit fields of the register facilitate software identification of the exact version of the
hardware peripheral incorporated into a system. The core driver can take advantage of this
read-only value to verify that the software is matched to the correct version of the
hardware.
NETWORK_PATH_DIFFERENTIAL (0x028) Register
Set the maximum delay between primary and secondary link for the core to operate in
seamless switching mode. The value is based on a 27MHz clock tick.
LogiCORE IP SMPTE 2022-5/6 RX v4.0
PG033 October 1, 2014
www.xilinx.com
Chapter 2: Product Specification
Send Feedback
27
Need help?
Do you have a question about the SMPTE 2022-5/6 and is the answer not in the manual?
Questions and answers