Mitsubishi Electric melsec q00ujcpu User Manual page 542

Programmable controller
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Number
Name
Meaning
Standby system
Error code of error
SD1649
error cancel
to be cleared
command
Other system
Other system
SD1650
operating
operating
information
information
Network module
Network module
head address,
head address,
which requested
which requested
SD1690
system
system switching
switching on
on host (control)
host (control)
system
system
*2 : Shows the special register (SD
Table12.35 Special register
Explanation
• Stores the error code of the error to be cleared by clearing a standby
system error.
• Stores the error code of the error to be cleared into this register and turn
SM1649 from OFF to ON to clear the standby system error.
• The value in the lowest digit (1 place) of the error code is ignored when
stored into this register.
(By storing 4100 in this register and resetting the error, errors 4100 to
4109 can be cleared.)
Stores the operation information of the other system CPU module in the
following format.
"00FF
" I stored when a communication error occurs, or when in debug
H
mode.
b15
to
b8
b7
to
b4
0
SD1650
0:No error
1:Continue error
2:Stop error
F:Communication with
other system
disabled
(
)
0:RUN
2:STOP
3:PAUSE
F:Communication with
other system
disabled
(
)
Note : A communication error is caused by the following:.
• When the power supply is switched off, or when the other system is
reset.
• H/W error occurs on either of system A or B.
• WDT error occurs.
• Tracking cable is not connected.
• Tracking cable is disconnected or damaged.
• Stores head address of network module which a system switch request
was initiated, using the following format.
• Turns off automatically by system, after network error is reset by user.
b15
to
b11
to
0
SD1690
0/1
0/1
• Please refer to SD1590 which stores the corresponding head address of
network module on host system.
) for the host system CPU.
CHAPTER12 PECIAL RELAY LIST AND SPECIAL REGISTER LIST
S(Every END)
b3 b0
to
: Communication
with other system
disabled, debug
mode
Each bit
b1 b0
0:OFF
0
1:ON
Module 0:
CPU module is
invalid as it is 2-
slot model
S(Every END)
Module 1:
Module on the
right side of the
to
CPU module
Module11:
Module at the
rightmost end of
the 12-slot base
(Q312B)
Corres-
ponding
Set by
Corresponding
ACPU
(When Set)
CPU
SD
*2
S(Every END)
QnPRH
12 - 76
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3
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