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Number
Name
Block information
using multiple CPU
OFF : Block is secured
high-speed
SM796
ON : Block set by SD796
transmission
dedicated instruction
(for CPU No.1)
Block information
using multiple CPU
OFF : Block is secured
high-speed
SM797
ON : Block set by SD797
transmission
dedicated instruction
(for CPU No.2)
Block information
using multiple CPU
OFF : Block is secured
high-speed
SM798
ON : Block set by SD798
transmission
dedicated instruction
(for CPU No.3)
Block information
using multiple CPU
OFF : Block is secured
high-speed
SM799
ON : Block set by SD799
transmission
dedicated instruction
(for CPU No.4)
*7: The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
(8) Debug
Number
Name
OFF : Not ready
SM800
Trace preparation
ON : Ready
OFF : Suspend
SM801
Trace start
ON : Start
Trace execution in
OFF : Suspend
SM802
progress
ON : Start
SM803
Trace trigger
OFF
OFF : Not after trigger
SM804
After trace trigger
ON : After trigger
OFF : Not completed
SM805
Trace completed
ON : End
OFF : Normal
SM826
Trace error
ON : Errors
ON : Forced registration
Forced registration
SM829
specification of trace
OFF : Forced registration
setting
*1: The Universal model QCPU except the Q00UJCPU.
Table12.8 Special relay
Meaning
• Turns ON when the number of the remaining blocks
of the dedicated instruction transmission area used
for the multiple CPU high-speed transmission
dedicated instruction(target CPU= CPU No.1) is less
than the number of blocks specified by SD796.
cannot be secured
Turns ON at instruction execution. Turns OFF when
the empty area exists at END processing.
• Turns ON when the number of the remaining blocks
of the dedicated instruction transmission area used
for the multiple CPU high-speed transmission
dedicated instruction (target CPU= CPU No.2) is less
than the number of blocks specified by SD797.
cannot be secured
Turns ON at instruction execution. Turns OFF when
the empty area exists at END processing.
• Turns ON when the number of the remaining blocks
of the dedicated instruction transmission area used
for the multiple CPU high-speed transmission
dedicated instruction (target CPU= CPU No.3) is less
than the number of blocks specified by SD798.
cannot be secured
Turns ON at instruction execution. Turns OFF when
the empty area exists at END processing.
• Turns ON when the number of the remaining blocks
of the dedicated instruction transmission area used
for the multiple CPU high-speed transmission
dedicated instruction(target CPU= CPU No.4) is less
than the number of blocks specified by SD799.
cannot be secured
Turns ON at instruction execution. Turns OFF when
the empty area exists at END processing.
Table12.9 Special relay
Meaning
• Switches ON when the trace preparation is
completed
• Trace is started when this relay switches ON.
• Trace is suspended when this relay switches OFF.
(All related special Ms switches OFF.)
• Switches ON during execution of trace.
• Trace is triggered when this relay switches from OFF
to ON. (Identical to TRACE instruction execution
ON: Start
status)
• Switches ON after trace is triggered.
• Switches ON at completion of trace
• Switches ON if error occurs during execution of trace
• Even when the trace condition or the trigger
condition is established, the sampling trace setting
enabled
can be set to the CPU module by turning SM829 ON
and registering the sampling trace setting by GX
disabled
Developer.
CHAPTER12 SPECIAL RELAY LIST AND SPECIAL REGISTER LIST
Explanation
(When Set)
S (When
instruction/END
processing
executed)
S (When
instruction/END
processing
executed)
S (When
instruction/END
processing
executed)
S (When
instruction/END
processing
executed)
Explanation
(When Set)
S (Status change)
S (Status change)
S (Status change)
S (Status change)
S (Status change)
Corres-
Set by
ponding
Corresponding
ACPU
CPU
M9
New
New
*7
QnU
New
New
Corres-
ponding
Set by
Corresponding
ACPU
CPU
M9
New
U
M9047
M9046
Qn(H)
QnPH
U
M9044
QnPRH
*1
QnU
New
M9043
New
U
New
*1
QnU
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