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Number
Name
Meaning
b0 to b14:
0: Do not
refresh
Refresh
1: Refresh
processing
b15 bit
selection when
0: communication
SD778
the COM/
with peripheral
CCOM
device is
instruction is
executed
executed
1: communication
with peripheral
device is
nonexecuted
SD781
Mask pattern of
to
IMASK
Mask pattern
SD793
instruction
SD781
Mask pattern of
to
IMASK
Mask pattern
SD785
instruction
SD794
PID limit setting
0: With limit
to
(for incomplete
1: Without limit
SD795
derivative)
PID limit setting
0: With limit
SD794
(for incomplete
1: Without limit
derivative)
*9: Function version is B or later.
*13: The module whose first 5 digits of serial No. is "09012" or later.
Table12.24 Special register
Explanation
• Selects whether or not the data is refreshed when the COM, CCOM
instruction is executed.
• Designation of SD778 is made valid when SM775 turns ON.
b15
b14
to
b6
b5
b4
b3
b2
SD778
0
0/1
0/1
0/1
0/1 0/1
• Stores the mask patterns masked by the IMASK instruction as follows:
b15
l63
SD781
to
SD782
l79
to
to
l255
SD793
to
(The Q00UJCPU, Q00UCPU, and Q01UCPU cannot use the special
registers SD786 to SD793.)
• Stores the mask patterns masked by the IMASK instruction as follows:
b15
l63
SD781
to
l79
SD782
to
to
to
l127
SD785
to
• Specify the limit of each PID loop as shown below.
b15
SD794
Loop16
to
SD795
Loop32
to
• Specify the limit of each PID loop as shown below.
b15
to
b8
b7
Loop8
SD794
CHAPTER12 PECIAL RELAY LIST AND SPECIAL REGISTER LIST
Set by
(When Set)
b1
b0
0/1
0/1
I/O refresh
CC-Link refresh
Refresh of
MELSECNET/H and
CC-Link IE controller
network
Automatic refresh of
intelligent function
U
modules
Auto refresh using
QCPU standard area of
multiple CPU system and
reading input/output from
group outside.
Auto refresh using the
multiple CPU high speed
transmission area of
multiple CPU system
Execution/non-
execution of
communication with
CPU module
b1
b0
l49
l48
l65
l64
S (During
execution)
l241
l240
b1
b0
l49
l48
S (During
l65
l64
execution)
l113
l112
b1
b0
U
Loop2
Loop1
Loop18
Loop17
b1
b0
U
Loop2
Loop1
to
Corres-
ponding
Corresponding
ACPU
CPU
D9
New
QnU
Qn(H)
QnPH
New
QnPRH
QnU
New
Q00J/Q00/Q01
*13
Qn(H)
New
QnPRH
QnU
New
*9
Q00J/Q00/Q01
12 - 60
1
2
3
12
6
7
8
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