(2) Timer counter output enable flags (TOE0, TOE1)
Timer counter output enable flags TOE0 and TOE1 enable or disable output to the PTO0 and PTO1 pins in
the timer out F/F (TOUT F/F) status.
The timer out F/F is inverted by a match signal from the comparator. When bit 3 (timer start command bit)
of timer counter mode register TM0 or TM1 is set to "1", the timer out F/F is cleared to "0".
TOE0, TOE1, and timer out F/F are cleared to "0" when the RESET signal is asserted.
Figure 6-29. Format of Timer Counter Output Enable Flag
Address
FA2H
TOE0
FAAH
TOE1
132
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
Channel 0
Channel 1
User's Manual U10676EJ3V0UM
Timer counter output enable flag (W)
0
Disabled
1
Enabled