36-Bit Destinations-Cc Bit Set; 20-Bit Destinations-Cc Bit Cleared - Motorola DSP56800 Manual

Data Arithmetic Logic Unit
3.6.2 36-Bit Destinations—CC Bit Set
Most arithmetic instructions generate a result for a 36-bit accumulator. When condition codes are being
generated for this case and the CC bit is set, condition codes are generated using only the 32 bits of the
accumulator located in the MSP and LSP. There may be values in the extension registers, but the contents
of the extension register are ignored. It is effectively the same as if there is no extension register. Examples
of instructions in this category are ADC, ADD, ASL, CMP, MAC, MACR, MPY, MPYR, NEG, NORM,
and RND.
The condition codes for 32-bit destinations (CC equals one) are computed as follows:
• N is set if bit 31 of the corresponding accumulator is set.
• Z is set if bits 31–0 of the corresponding accumulator are all cleared.
• V is set if overflow has occurred in the 32-bit result.
• C is set if a carry (borrow) has occurred out of bit 31 of the result.
3.6.3 20-Bit Destinations—CC Bit Cleared
Two arithmetic instructions generate a result for the upper two portions of an accumulator, the MSP and
the extension register, leaving the LSP of the accumulator unchanged. When condition codes are being
generated for this case and the CC bit is cleared, condition codes are generated using the 20 bits in the
upper two portions of the accumulator. The two instructions in this category are DECW and INCW.
The condition codes for DECW and INCW (CC equals zero) are computed as follows:
• N is set if bit 35 of the corresponding accumulator is set except during saturation. During a
saturation condition, the V (overflow) bit is set and the N bit is not set.
• Z is set if bits 35–16 of the corresponding accumulator are all cleared.
• V is set if overflow has occurred in the 20-bit result.
• C is set if a carry (borrow) has occurred out of bit 35 of the result.
3.6.4 20-Bit Destinations—CC Bit Set
Two arithmetic instructions generate a result for the upper two portions of an accumulator, the MSP and
the extension register, leaving the LSP of the accumulator unchanged. When condition codes are being
generated for this case and the CC bit is set, the bits in the extension register and the LSP of the
accumulator are not used to calculate condition codes. The two instructions in this category are DECW and
INCW.
The condition codes for 16-bit destinations (CC equals one) are computed as follows:
• N is set if bit 31 of the corresponding accumulator is set.
• Z is set if bits 31–16 of the corresponding accumulator are all cleared.
• V is set if overflow has occurred in the 16-bit result.
• C is set if a carry (borrow) has occurred out of bit 31 of the result.
3-34 DSP56800 Family Manual