Operating Mode Bits (Mb And Ma)—Bits 1–0; Table 5-2 Program Rom Operating Modes; Figure 5-5 Operating Mode Register (Omr) Format - Motorola DSP56800 Manual

Program Controller
When a bit of the OMR is changed by an instruction, a delay of one
instruction cycle is necessary before the new mode comes into effect.
OMR
Operating Mode
Register
Reset = $0000
Read/Write
NL—Nested Looping
CC—Condition Codes
SD—Stop Delay
R—Rounding
SA—Saturation
EX—External X Memory
MA,MB—Operating Mode
* Indicates reserved bits that are read as zero and should be written with zero for future compatibility
5.1.9.1 Operating Mode Bits (MB and MA)—Bits 1–0
The chip operating mode (MB and MA) bits (OMR bits 1 and 0) indicate the operating mode and memory
maps of a DSP chip that has an external bus. Possible operating modes for a program RAM part are shown
in Table 5-2.
MB MA Chip Operating Mode
0 0
0 1
1 0
1 1
The exact implementation of the mode bits, and the number of modes supported, depends on the specific
DSP56800 Family device being used. See the appropriate user's manual for more detailed information on
the operating modes.
The bootstrap modes are used to initially load an on-chip program RAM upon exiting reset from external
memory or through a peripheral. Operating modes 0 and 1 typically would be different for a program ROM
part because no bootstrapping operation is required for a ROM part. An example of possible operating
modes for a program ROM part are shown in Table 5-3 on page 5-11.
5-10
15 14 13 12 11
NL
* * * *
Figure 5-5. Operating Mode Register (OMR) Format
Table 5-2. Program ROM Operating Modes
Bootstrap 0
Bootstrap 1
Normal Expanded
Development
DSP56800 Family Manual
NOTE:
OMR
10 9 8 7 6
CC SD
* * *
Reset Vector
BOOTROM P:$0000
(Boot from External Bus)
BOOTROM P:$0000
(Boot from Peripheral)
External Pmem P:$E000
External Pmem P:$0000
5 4 3 2 1
R SA EX MB
*
AA0013
Program Memory
Configuration
Internal P-RAM is write only
Internal P-RAM is write only
Internal Pmem enabled
Internal Pmem disabled
0
MA