Table of Contents
Advertisement
Chapter 3
Data Arithmetic Logic Unit
This chapter describes the architecture and the operation of the data arithmetic logic unit (ALU), the block
where the multiplication, logical operations, and arithmetic operations are performed. (Addition can also
be performed in the address generation unit, and the bit-manipulation unit can perform logical operations.)
The data ALU contains the following:
•
Three 16-bit input registers (X0, Y0, and Y1)
•
Two 32-bit accumulator registers (A and B)
•
Two 4-bit accumulator extension registers (A2 and B2)
•
An accumulator shifter (AS)
•
One data limiter
•
One 16-bit barrel shifter
•
One parallel (single cycle, non-pipelined) multiply-accumulator (MAC) unit
Multiple buses in the data ALU perform complex arithmetic operations (such as a multiply-accumulate
operations) in parallel with up to two memory transfers. A discussion of fractional and integer data
representations; signed, unsigned, and multi-precision arithmetic; condition code generation; and the
rounding modes used in the data ALU are also described in this section.
The data ALU can perform the following operations in a single instruction cycle:
•
Multiplication (with or without rounding)
•
Multiplication with inverted product (with or without rounding)
•
Multiplication and accumulation (with or without rounding)
•
Multiplication and accumulation with inverted product (with or without rounding)
•
Addition and subtraction
•
Compares
•
Increments and decrements
•
Logical operations (AND, OR, and EOR)
•
One's-complement
•
Two's-complement (negation)
•
Arithmetic and logical shifts
•
Rotates
•
Multi-bit shifts on 16-bit values
•
Rounding
•
Absolute value
Data Arithmetic Logic Unit
3-1
- Quick Links:
- Dsp56800 Family Architecture
Hide quick links:
Advertisement
Chapters
Table of Contents
