Table A-9 Condition Code Summary - Motorola DSP56800 Manual

The "Comments" column in the table is also used to report if any of the upper bits in the status register are
modified. These are not status bits because they do not lie in the status portion of the status register, but
rather in the control portion. Sometimes these bits are also affected by instructions. Examples include the
interrupt mask bits, I1 and I0, and the looping bits, LF and NL (NL lies in the OMR register).
The following instruction mnemonics are not found in Table A-9: ANDC, EORC, NOTC and ORC. This is
because each of these is an alias for another instruction and not an instruction in its own right. To
determine condition code calculation for each of these, determine the instructions to which these
mnemonics are mapped (see Section 6.5.1, "ANDC, EORC, ORC, and NOTC Aliases," on page 6-12) and
look at the condition code information for the corresponding real instructions.
Instruction SZ
ABS *
ADC -
ADD *
AND -
ASL *
ASLL -
ASR *
ASRAC -
ASRR -
Bcc -
BFCHG -
BFCLR -
BFSET -
BFTSTH -
BFTSTL -
BRA -
BRCLR -
BRSET -
CLR *
CMP *
DEBUG -
DEC(W) *
DIV -
Table A-9. Condition Code Summary
L E U N
CT *36 *36 *36
C *36 *36 *36
CT *A *A *A
- - - *16
CT *A *A *A
- - - (18)
T *A *A *A
- - - (16)
- - - *32
- - - -
T - - -
T - - -
T - - -
T - - -
T - - -
- - - -
T - - -
T - - -
CT *36 *36 *36
CT *A *A *A
- - - -
CT *B *B *B
C - - -
Instruction Set Details
Z V C
*36 *36 -
*36 *36 *36
*A *A *A
*16 =0 -
*A (1) (2)
*32 - -
*A =0 (3)
*36 - -
*32 - -
- - -
- - (4)
- - (4)
- - (4)
- - (4)
- - (5)
- - -
- - (5)
- - (4)
*36 *36 - Never overflows
*A *A *A
- - -
*B *B *B
- (1) (6)
Comments
A-13