Motorola DSP56800 Manual page 439

Index
A
,
A accumulator 3-2 3-4
A0, see A accumulator
A1, see A accumulator
A2 accumulator extension register 3-2
ABS A-28
Absolute Value ABS A-28
accumulator extension register (A2 or B2) 3-4
accumulator extension registers 3-2
accumulator registers 3-2
,
accumulator shifter 3-2
accumulator sign-extend 8-7
ADC A-30
ADD A-32
Add ADD A-32
Add Long with Carry ADC A-30
addition
fractional 3-18
multi-precision 3-23
unsigned 3-22
Address Generation Unit (AGU) 2-3
address registers (R0-R3) 4-4
incrementer/decrementer unit 4-5
Modifier Register (M01) 4-5
modulo arithmetic unit 4-5
Offset Register (N) 4-4
Stack Pointer Register (SP) 4-4
address register indirect modes 4-7
,
addressing modes 4-1 4-6
addressing modes summary 4-23
AGU, see Address Generation Unit (AGU) 4-1
ALU, see Data Arithmetic Logic Unit (ALU)
analog signal processing 1-5
analog-to-digital 1-6
AND A-35
ANDC A-36
arithmetic
division 3-21
multiplication 3-19
,
unsigned 3-22 3-36
arithmetic instructions 6-6
Arithmetic Right Shift with Accumulate ASRAC A-44
Arithmetic Shift Left ASL A-38
Arithmetic Shift Right ASR A-42
array indexes 8-26
ASL A-38
ASLL A-40
,
3-4
3-6
,
4-1
,
A-6
ASR A-42
ASRAC A-44
ASRR A-46
B
,
B accumulator 3-2
B0, see B accumulator
B1, see B accumulator
B2 accumulator extension register 3-2
,
barrel shifter 3-2 3-5
Bcc A-48
BEC 8-4
benchmarks B-1
BES 8-4
BFCHG A-50
BFCLR A-52
BFSET A-54
BFTSTH A-56
BFTSTL A-58
bit-manipulation instructions 6-8
bit-manipulation unit 2-5
BLC 8-4
BLS 8-4
BMI 8-4
bootstrap memory 2-8
boundary scan cell 9-1
BPL 8-4
BR1CLR operation 8-3
BR1SET operation 8-3
BRA A-59
Branch BRA A-59
Branch Conditionally Bcc A-48
Branch if Bits Clear BRCLR A-60
Branch if Bits Set BRSET A-62
branching techniques, software 8-2
BRCLR A-60
BRSET A-62
bus unit 2-5
BVC 8-4
BVS 8-4
C
,
C condition bit 5-7
CC, see condition code (CC) bit
CCR, see Condition Code Register (CCR)
CGDB, see core global data bus (CGDB)
Clear Accumulator CLR A-64
Index
3-4
A-10
Index-i