Motorola DSP56800 Manual page 311

EORC
Operation:
#xxxx ⊕ X:<ea> → X:<ea>
#xxxx ⊕ D → D
where ⊕ denotes the logical exclusive OR operator
Implementation Note:
This instruction is an alias to the BFCHG instruction, and assembles as BFCHG with the 16-bit imme-
diate value as the bit mask. This instruction will disassemble as a BFCHG instruction.
Description: Logically exclusive OR a 16-bit immediate data value with the destination operand (D) and store the
results back into the destination. C is also modified as described below. This instruction performs a
read-modify-write operation on the destination and requires two destination accesses.
Example:
EORC
Before Execution
X:$FFE0
SR
Explanation of Example:
Prior to execution, the 16-bit X memory location X:$FFE0 contains the value $0010. Execution of the
instruction tests the state of the bits 4, 8, and 9 in X:$FFE0; does not set C (because all of the CCR bits
were not set); and then complements the bits.
Condition Codes Affected:
15 14
LF *
For destination operand SR:
For other destination operands:
Logical Exclusive OR Immediate
#$0FF0,X:<<$FFE0; Exclusive OR with immediate data
5555
0000
MR
13 12 11 10 9
* * * * I1
? — Changed if specified in the field
C — Set if all bits specified by the mask are set
Instruction Set Details
Assembler Syntax:
EORC #iiii,X:<ea>
EORC #iiii,D
After Execution
X:$FFE0
SR
CCR
8 7 6 5 4
I0 SZ L E U
EORC
5AA5
0000
3 2 1 0
C
N Z V
A-81