Figure 7-7 Interrupting A Rep Instruction; Wait Processing State - Motorola DSP56800 Manual

Interrupt
Synchronized and
Recognized
as Pending
Interrupts
Re-enabled
i= Interrupt Instruction
n= Normal Instruction
Interrupt Control Cycle 1
Interrupt Control Cycle 2
Fetch
Decode
Execute
Instruction Cycle Count
i = Interrupt
ii = Interrupt Instruction Word
n = Normal Instruction Word
i% = Interrupt Rejected
7.4

Wait Processing State

The WAIT instruction brings the processor into the wait processing state, which is one of two low
power-consumption states. Asserting any valid interrupt request higher than the current processing level
(as defined by the I1 and I0 bits in the status register) releases the DSP from the wait state. In the wait state
the internal clock is disabled from all internal circuitry except the internal peripherals. All internal
processing is halted until an unmasked interrupt occurs or until the DSP is reset.
Main
Program
Fetches
n1 REP m
n2
n3
n4
n5
n6
(a) Instruction Fetches from Memory
Interrupt Synchronized and
Recognized as Pending
i
i%
REP n2
REP REP REP
REP REP
1 2 3 4
(b) Program Controller Pipeline
Figure 7-7. Interrupting a REP Instruction
Interrupts and the Processing States
Repeat m
Times
i1
i2
Interrupts Re-enabled
i
i
n3
n2 n2 n2 n2
REP n2 n2 n2
5 6 7 8
Wait Processing State
n2
n2
n2
n2
Instruction N2
Replaced Per
The REP Instruction
Interrupt
Service Routine Fetches
(From Between P:$0000 And
P:$003F)
ii1 ii2 n5 n6
JSR JSR JSR JSR
n2 JSR JSR JSR
9 10 11 12
AA0071
7-17