Lsr - Motorola DSP56800 Manual

LSR

Operation:
(see following figure)
0
Unch.
D2
Description: Logically shift 16 bits of the destination operand (D) 1 bit to the right and store the result in the desti-
nation. If the destination is a 36-bit accumulator, the result is stored in the MSP of the accumulator (A1
or B1), and the remaining portions of the accumulator (A2, B2, A0, B0) are not modified.The LSB of
the destination (bit 16 if the destination is a 36-bit accumulator) prior to the execution of the instruction
is shifted into C, and zero is shifted into the MSB of D1 (bit 31if the destination is a 36-bit accumula-
tor).
Example:
LSR
Before Execution
F 0001
B2 B1
SR
0300
Explanation of Example:
Prior to execution, the 36-bit B accumulator contains the value $F:0001:00AA. Execution of the
LSR B instruction shifts the 16-bit value in the B1 register 1 bit to the right and stores the result back
in the B1 register. C is set by the operation because bit 0 of B1 was set prior to the execution of the
instruction. The Z bit of CCR (bit 2) is also set because the result in B1 is zero.
Logical Shift Right
Assembler Syntax:
LSR
Unchanged
D1 D0
B ; divide B1 by 2 (B1 considered unsigned)
00AA
B0
Instruction Set Details
D
C (no parallel move)
After Execution
F 0000
B2 B1
SR
0305
LSR
00AA
B0
A-97