Motorola DSP56800 Manual page 402

TSTW
Operation:
S - 0 (no parallel move)
Description: Compare 16 bits of the specified source register or memory location with zero, and set the condition
codes accordingly. No result is stored, although the condition codes are updated.
Example:
TSTW
Before Execution
X:$0007
SR
Explanation of Example:
Prior to execution, location X:$0007contains the value $FC00 and the 16-bit SR contains the value
$0300. Execution of the instruction compares the value in memory location X:$0007 with zero and up-
dates the CCR accordingly. The value of location X:$0007 is not affected.
Note:
This instruction does not set the same set of condition codes that the TST instruction does. Both in-
structions correctly set the V, N, Z, and C bits, but TST sets the E bit and TSTW does not. This is a
16-bit test operation when done on an accumulator (A or B), where limiting is performed if appropriate
when reading the accumulator.
Condition Codes Affected:
15 14
LF *
A-172
Test Register or Memory
X:$0007
FC00
0300
MR
13 12 11 10 9
* * * * I1
N — Set if bit 15 (bit 31 of A or B) of result is set
Z — Set if result equals zero
V — Always cleared
C — Always cleared
DSP56800 Family Manual
Assembler Syntax:
TSTW
; set condition codes using X:$0007
After Execution
X:$0007
SR
CCR
8 7 6 5 4
I0 SZ L E U
TSTW
S (no parallel move)
FC00
0308
3 2 1 0
N Z V C