Program Controller; Architecture And Programming Model - Motorola DSP56800 Manual

Chapter 5

Program Controller

The program controller unit is one of the three execution units in the central processing module. The
program controller performs the following:
• Instruction fetching
• Instruction decoding
• Hardware DO and REP loop control
• Exception (interrupt) processing
This section covers the following:
• The architecture and programming model of the program controller
• The operation of the software stack
• A discussion of program looping
Details of the instruction pipeline and the different processing states of the DSP chip, including reset and
interrupt processing, are covered in Chapter 7, "Interrupts and the Processing States."
5.1

Architecture and Programming Model

A block diagram of the program controller is shown in Figure 5-1 on page 5-2, and its corresponding
programming model is shown in Figure 5-2 on page 5-3. The programmer views the program controller as
consisting of five registers and a hardware stack (HWS). In addition to the standard program flow-control
resources such as a program counter (PC) and status register (SR), the program controller features registers
dedicated to supporting the hardware DO loop instruction—loop address (LA), loop counter (LC), and the
hardware stack—and an operating mode register (OMR) defining the DSP operating modes.
The blocks and registers within the program controller are explained in the following subsections.
Program Controller 5-1