A.3 Addressing Modes; A.4 Condition Code Computation - Motorola DSP56800 Manual

A.3 Addressing Modes
The addressing modes are grouped into three categories:
• Register direct—directly references the registers on the chip
• Address register indirect—uses an address register as a pointer to reference a location in memory
• Special—includes direct addressing, extended addressing, and immediate data
These addressing modes are described in the following discussion and summarized in Table 4-5 on
page 4-9.
All address calculations are performed in the address ALU to minimize execution time and loop overhead.
Addressing modes specify whether the operands are in registers, in memory, or in the instruction itself
(such as immediate data) and provide the specific address of the operands.
The register-direct addressing mode can be subclassified according to the specific register addressed. The
data registers include X0, Y1, Y0, Y, A2, A1, A0, B2, B1, B0, A, and B. The control registers include
HWS, LA, LC, OMR, SR, CCR, and MR. The address registers include R0, R1, R2, R3, SP, N, and M01.
Address-register-indirect modes use an address register Rn (R0–R3) or the stack pointer (SP) to point to
locations in X and P memory. The contents of the Rn is the effective address (ea) of the specified operand,
except in the indexed-by-offset or indexed-by-displacement mode, where the effective address (ea) is
(Rn+Nn) or (Rn+xxxx), respectively. Address-register-indirect modes use an address modifier register
M01 to specify the type of arithmetic to be used to update the address register R0 and optionally R1. R2
and R3 always use linear arithmetic. If an addressing mode specifies the address offset register (N), it is
used to update the corresponding Rn. This unique implementation is extremely powerful and allows the
user to easily address a wide variety of DSP-oriented data structures. All address-register-indirect modes
use at least one Rn and sometimes N and the modifier register (M01), and the double X memory read uses
two address registers, one for the first X memory read and one for the second X memory read. Only R3 can
be used for this second X memory read, and R3 is always updated using linear arithmetic.
The special addressing modes include immediate and absolute addressing modes as well as implied
references to the program counter (PC), the software stack, the hardware stack (HWS), and the program
(P) memory.
The addressing mode selected in the instruction word is further specified by the contents of the address
modifier register M01. The modifier selects whether linear or modulo arithmetic is performed. The
programming of this register is summarized in Table 4-9 on page 4-27.
A.4 Condition Code Computation
The bits in the Condition Code Register (CCR) are set to reflect the status of the processor after certain
instructions are executed. The CCR bits are affected by data ALU operations, bit-field manipulation
instructions, the TSTW instruction, parallel move operations, and by instructions that directly reference the
CCR register.
In addition, the computation of some condition code bits is affected by the OMR's Saturation (SA) and
condition code (CC) bits. The SA bit enables the MAC Output Limiter, which can alter the results of
computations and thus the condition code bits affected. The CC bit specifies whether condition codes are
generated using the information in the extension register. See Section A.4.2, "Effects of the Operating
Mode Register's SA Bit," and Section A.4.3, "Effects of the OMR's CC Bit," for more information.
A-6 DSP56800 Family Manual