Motorola DSP56800 Manual page 301

DIV
Operation:
(see following figure)
D[35] ⊕ S[15] = 1
If
Then
Else
Description: This instruction is a divide iteration used to calculate 1 bit of the result of a division. After the correct
number of iterations, this will divide the destination operand (D)—dividend or numerator—by the
source operand (S)—divisor or denominator—and store the result in the destination accumulator. The
32-bit dividend must be a positive value that is correctly sign extended to 36 bits and is stored in the
full 36-bit destination accumulator. The 16-bit divisor is a signed value and is stored in the source op-
erand. (Division of signed numbers is handled using the techniques in Section 8.4, "Division," on page
8-13.) This instruction can be used for both integer and fractional division. Each DIV iteration calcu-
lates one quotient bit using a non-restoring division algorithm (see the description that follows). After
execution of the first DIV instruction, the destination operand holds both the partial remainder and the
formed quotient. The partial remainder occupies the high-order portion of the destination accumulator
D and is a signed fraction. The formed quotient occupies the low-order portion of the destination ac-
cumulator D (A0 or B0) and is a positive fraction. One bit of the formed quotient is shifted into the
LSB of the destination accumulator at the start of each DIV iteration. The formed quotient is the true
quotient if the true quotient is positive. If the true quotient is negative, the formed quotient must be
negated. For fractional division, valid results are obtained only when |D| < |S|. This condition ensures
that the magnitude of the quotient is less than one (is fractional) and precludes division by zero.
The DIV instruction calculates one quotient bit based on the divisor and the previous partial remainder.
To produce an N-bit quotient, the DIV instruction is executed N times, where N is the number of bits
of precision desired in the quotient (1 < N < 16). Thus, for a full precision (16-bit) quotient, 16 DIV
iterations are required. In general, executing the DIV instruction N times produces an N-bit quotient
and a 32-bit remainder, which has (32 - N) bits of precision and whose N MSBs are zeros. The partial
remainder is not a true remainder and must be corrected (due to the non-restoring nature of the division
algorithm) before it may be used. Therefore, once the divide is complete, it is necessary to reverse the
last DIV operation and restore the remainder to obtain the true remainder. The DIV instruction uses a
non-restoring division algorithm that consists of the following operations:
1) Compare the source and destination operand sign bits. An exclusive OR operation is performed on
bit 35 of the destination operand and bit 15 of the source operand.
2) Shift the partial remainder and the quotient. The 36-bit destination accumulator is shifted 1 bit to
the left. C is moved into the LSB (bit 0) of the accumulator.
3) Calculate the next quotient bit and the new partial remainder. The 16-bit source operand (signed di-
visor) is either added to or subtracted from the MSP of the destination accumulator (A1 or B1), and the
result is stored back into the MSP of the destination accumulator. If the result of the exclusive OR op-
eration described previously was one (that is, the sign bits were different), the source operand S is add-
ed to the accumulator. If the result of the exclusive OR operation was zero (that is, the sign bits were
the same), the source operand S is subtracted from the accumulator. Due to the automatic sign exten-
sion of the 16-bit signed divisor, the addition or subtraction operation correctly sets C with the next
quotient bit.
Divide Iteration
D2 D1
D2 D1
Instruction Set Details
Assembler Syntax:
DIV
C;
D0
C;
D0
S,D (no parallel move)
D1 + S D1
D1 - S D1
DIV
A-71