Fujitsu SPARC Enterprise M8000 Service Manual page 501

In case of SPARC64 VI processor:
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2.28 GHz, L2 cache 5M bytes/2.4 GHz, L2 cache 6M bytes
In case of SPARC64 VII processor:
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2.52 GHz, L2 cache 6M bytes/2.88 GHz, L2 cache 6M bytes
In case of SPARC64 VII+ processor:
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3.0 GHz, L2 cache 12M bytes
Note – To make maximum use of the 12M bytes L2 cache memory with SPARC64 VII+
processors, it is necessary to use a certain type of CMU (CMU_C) and mount the CPU
modules which consist entirely of the SPARC64 VII+ processors. If the CPU modules of
different frequencies are mixed on CMU_C, the usable L2 cache memory is limited to 6M
bytes. Also, if you use other types of CMU (CMU_A or CMU_B) and mount the CPU
modules which consist entirely of the SPARC64 VII+ processor, the usable L2 cache
memory is limited to 6M bytes.
For the bus connecting CPU and SC, a high-speed link is used.
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The CPU module has a label bearing the printed component number and manufacture's
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serial number.
Appendix B Components B-7