Register Bits Used To Set The Srg Clock Mode (Choose An Input Clock) - Texas Instruments TMS320VC5501 Reference Manual

Setting the SRG Clock Mode (Choosing an Input Clock)
7.23 Setting the SRG Clock Mode (Choosing an Input Clock)
Figure 7−26. Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)
PCR
15
SRGR2
15 14 13 12
CLKSM
R/W-1
Legend: R = Read; W = Write; -n = Value after reset
Table 7−28. Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)
Register Bit Name
PCR 7 SCLKME
SRGR2 13 CLKSM
7.23.1 About the SRG Clock Mode
7-40 Receiver Configuration
The bits shown in Figure 7−26 and described in Table 7−28 determine the
source for the SRG clock. Not all C55x devices have a CLKS pin; check the
device-specific data manual.
Function
Sample Rate Generator Clock Mode
SCLKME = 0
CLKSM = 0
SCLKME = 0
CLKSM = 1
SCLKME = 1
CLKSM = 0
SCLKME = 1
CLKSM = 1
The sample rate generator can produce a clock signal (CLKG) for use by the
receiver, the transmitter, or both, but CLKG is derived from an input clock.
Table 7−28 shows the four possible sources of the input clock.
8 7 6
SCLKME
R/W-0
Sample rate generator clock derived from CLKS pin
Sample rate generator clock derived from McBSP internal
input clock (This is the condition forced by a DSP reset.)
Sample rate generator clock derived from CLKR pin
Sample rate generator clock derived from CLKX pin
0
0
SPRU592E