Destination Of Endianness Manager (Out_Order = 0); Trellis Stage Ordering Of Hard Decisions In 32-Bit Word (Out_Order = 1); Data Source = Kernel; Data Destination = Edma3 En = 0 (Big-Endian Mode) - Texas Instruments TURBO-DECODER COPROCESSOR 2 TMS320C6457 DSP User Manual

Endianness
63 62
Stage Stage
N - 32 N - 33
4. OUT_ORDER = 1 EN = 1 (Little-Endian Mode)
Figure 78. Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1)
63 62
Stage Stage
N N - 1
Figure 79. Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1)
63 62
Stage Stage
N - 63 N - 62
Hard decisions are packed in a 32 bit word inside the TCP2. Data will be saved in word format (32 bits) in
the DSP.
They have to be swapped as described in
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
7.1.2 TCP_ENDIAN Register for Endianness Manager
TCP2 input/output data are of different widths and storage in the DSP memory subsystem will be different
whether they are saved in native or word format. However, EDMA3 will always read and write words.
There is a need to define a way of handling the data depending on whether they are saved in native or
words format. Table 33
TCP_ENDIAN programming (see
54 TMS320C6457 Turbo-Decoder Coprocessor 2
Figure 77. Destination of Endianness Manager (OUT_ORDER = 0)
32
Stage
N - 63
32
Stage
N - 31
32
Stage
N - 32
Table 32. Hard Decisions in DSP Memory
Address (hex bytes)
Base
Base + 4
Figure 80
Figure 80. Data Source = Kernel
HD1
R/W
Figure 81. Data Destination = EDMA3 EN = 0 (Big-Endian Mode)
HD0
R/W
summarizes the different data formats, as well as the memory-mapped register
Figure 82).
31
Stage
N
31
Stage
N - 32
31
Stage
N - 31
Data
HD0 (32 hard decisions)
HD1 (32 hard decisions)
and Figure 81.
8 7
8 7
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1 0
Stage Stage
N - 30 N - 31
1 0
Stage Stage
N - 62 N - 63
1 0
Stage Stage
N - 1 N
HD0
R/W
HD1
R/W
SPRUGK1 – March 2009
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