Overrun In The Receiver - Texas Instruments TMS320VC5501 Reference Manual

4.2 Overrun in the Receiver

4.2.1 Example of the Overrun Condition
SPRU592E
RFULL = 1 in SPCR1 indicates that the receiver has experienced overrun and
is in an error condition. RFULL is set when all of the following conditions are
met:
1) DRR1 has not been read since the last RBR-to-DRR copy (RRDY = 1).
2) RBR1 is full and an RBR-to-DRR copy has not occurred.
3) RSR1 is full and an RSR1-to-RBR copy has not occurred.
As described in section 2.5, McBSP Reception, data arriving on DR is
continuously shifted into RSR1 (for word length of 16 bits or smaller) or RSR2
and RSR1 (for word length larger than 16 bits). Once a complete word is
shifted into the RSR(s), an RSR-to-RBR copy can occur only if the previous
data in RBR1 has been copied to DRR1. The RRDY bit is set when new data
arrives in DRR1 and is cleared when that data is read from DRR1. Until
RRDY = 0, the next RBR-to-DRR copy will not take place, and the data is held
in the RSR(s). New data arriving on the DR pin is shifted into RSR(s), and the
previous content of the RSR(s) is lost.
You can prevent the loss of data if DRR1 is read no later than 2.5 cycles before
the end of the third word is shifted into the RSR1.
Important: If both DRRs are needed (word length larger than 16 bits), the CPU
or the DMA controller must read from DRR2 first and then from DRR1. As soon
as DRR1 is read, the next RBR-to-DRR copy is initiated. If DRR2 is not read
first, the data in DRR2 is lost.
Note that after the receiver starts running from reset, a minimum of three words
must be received before RFULL is set. Either of the following events clears the
RFULL bit and allows subsequent transfers to be read properly:
The CPU or the DMA controller reads DRR1.
-
The receiver is reset individually (RRST = 0) or as part of a DSP reset.
-
Another frame-sync pulse is required to restart the receiver.
Figure 4−1 shows the receive overrun condition. Because serial word A is not
read from DRR1 before serial word B arrives in RBR1, B is not transferred to
DRR1 yet. Another new word (C) arrives and RSR1 is full with this data. DRR1
is finally read, but not earlier than 2.5 cycles before the end of word C.
Therefore, new data (D) overwrites word C in RSR1. If DRR1 is not read in
time, the next word can overwrite D.
Overrun in the Receiver
McBSP Exception/Error Conditions 4-3