Sdram Status Register (Sdrstat); Ddr2 Memory Controller Registers Relative To Base Address 2000 0000H; Ddr2 Memory Controller Registers Relative To Base Address 01C4 2000H; Ddr2 Memory Controller Registers Relative To Base Address 01C4 0000H - Texas Instruments TMS320DM643 User Manual

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Table 22. DDR2 Memory Controller Registers Relative to Base Address 2000 0000h
Offset Acronym
4h SDRSTAT
8h SDBCR
Ch SDRCR
10h SDTIMR
14h SDTIMR2
20h PBBPR
C0h IRR
C4h IMR
C8h IMSR
CCh IMCR
E4h DDRPHYCR
F0h VTPIOCR
Table 23. DDR2 Memory Controller Registers Relative to Base Address 01C4 2000h
Offset Acronym
38h DDRVTPR
Table 24. DDR2 Memory Controller Registers Relative to Base Address 01C4 0000h
Offset Acronym
4Ch DDRVTPER
4.1

SDRAM Status Register (SDRSTAT)

The SDRAM status register (SDRSTAT) is shown in
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = value is indeterminate after reset
Bit Field Value
31-3 Reserved 0
2 PHYRDY
0
1
1-0 Reserved 0
SPRU986B – November 2007
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Register Description
SDRAM Status Register
SDRAM Bank Configuration Register
SDRAM Refresh Control Register
SDRAM Timing Register
SDRAM Timing Register 2
Peripheral Bus Burst Priority Register
Interrupt Raw Register
Interrupt Masked Register
Interrupt Mask Set Register
Interrupt Mask Clear Register
DDR PHY Control Register
VTP IO Control Register
Register Description
DDR VTP Register
Register Description
DDR VTP Enable Register
Figure 19. SDRAM Status Register (SDRSTAT)
Reserved
R-0
Table 25. SDRAM Status Register (SDRSTAT) Field Descriptions
Description
Reserved
DDR2 memory controller DLL ready. Reflects whether the DDR2 memory controller DLL is powered up
and locked.
DLL is not ready, either powered down, in reset, or not locked.
DLL is powered up, locked, and ready for operation.
Reserved
Figure 19 and described in
Reserved
R-4000h
DDR2 Memory Controller Registers
Section
Section 4.1
Section 4.2
Section 4.3
Section 4.4
Section 4.5
Section 4.6
Section 4.7
Section 4.8
Section 4.9
Section 4.10
Section 4.11
Section 4.12
Section
Section 4.13
Section
Section 4.14
Table 25.
3 2 1
PHYRDY Reserved
R-0 R-0
DDR2 Memory Controller
16
0
41